參數(shù)資料
型號(hào)： CYP15G0403DXB
廠商： Cypress Semiconductor Corp.
英文描述： Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
中文描述： 獨(dú)立時(shí)鐘四路HOTLink II收發(fā)器（獨(dú)立時(shí)鐘，四熱連接二收發(fā)器）
文件頁數(shù)： 27/43頁
文件大?。?/td> 744K
代理商： CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 27 of 43
CYP(V)(W)15G0403DXB AC Electrical Characteristics
Parameter
CYP(V)(W)15G0403DXB Transmitter LVTTL Switching Characteristics
Over the Operating Range
f
TS
TXCLKx Clock Cycle Frequency
t
TXCLK
TXCLKx Period=1/f
TS
t
TXCLKH[20]
TXCLKx HIGH Time
t
TXCLKL[20]
TXCLKx LOW Time
t
TXCLKR [20, 21, 22, 23]
TXCLKx Rise Time
t
TXCLKF [20, 21, 22, 23]
TXCLKx Fall Time
t
TXDS
Transmit Data Set-up Time to
TXCLKx
↑
(TXCKSELx
≠
0)
t
TXDH
Transmit Data Hold Time from TXCLKx
↑
(TXCKSELx
≠
0)
f
TOS
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
t
TXCLKO
TXCLKOx Period=1/f
TOS
t
TXCLKOD
TXCLKO Duty Cycle centered at 60% HIGH time
CYP(V)(W)15G0403DXB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx± Clock Output Frequency
t
RXCLKP
RXCLKx± Period = 1/f
RS
t
RXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate when
RXCKSELx = 0)
t
RXCLKR [20]
RXCLKx± Rise Time
t
RXCLKF [20]
RXCLKx± Fall Time
t
RXDv–[24]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx =
0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx =
0) (Half Rate)
t
RXDv+[24]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx =
0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx =0)
(Half Rate)
CYP(V)(W)15G0403DXB REFCLKx Switching Characteristics
Over the Operating Range
f
REF
REFCLKx Clock Frequency
t
REFCLK
REFCLKx Period = 1/f
REF
t
REFH
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
t
REFL
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
t
REFD[27]
REFCLKx Duty Cycle
t
REFR [20, 21, 22, 23]
REFCLKx Rise Time (20%–80%)
t
REFF[20, 21, 22, 23]
REFCLKx Fall Time (20%–80%)
Notes:
18. This parameter is 154 MHz for CYW15G0403DXB.
19. This parameter is 6.49 ns for CYW15G0403DXB.
20. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
21. The ratio of rise time to falling time must not vary by greater than 2:1.
22. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
23. All transmit AC timing parameters measured with 1 ns typical rise time and fall time.
24. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
25. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when TXRATEx = 1) or 1/(f
* 10) (when TXRATEx = 0). In an operating link this is equivalent to t
B
.
26. If REFCLKx is selected as receive interface clock (RXCKSELx=1), then this parameter has to be greater than or equal to 6.3 ns.
27. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLKx± duty
cycle cannot be as large as 30%–70%.
Description
Min.
Max
Unit
19.5
6.66
[19]
2.2
2.2
0.2
0.2
2.2
1.0
19.5
6.66
[19]
–1.9
150
[18]
51.28
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
1.7
1.7
150
[18]
51.28
0
9.75
6.66
[19]
–1.0
150
[18]
102.56
+1.0
MHz
ns
ns
0.3
0.3
1.2
1.2
ns
ns
ns
5UI – 2.0
[25]
5UI – 1.3
[25]
ns
5UI–1.8
[25]
ns
5UI – 2.6
[25]
ns
19.5
6.66
[19]
5.9
[26]
2.9
[20]
5.9
[26]
2.9
[20]
30
150
[18]
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
70
2
2
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