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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 7/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 7 of 43
Pin Descriptions
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
Transmit Path Data and Status Signals
TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]
LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
Transmit Data Inputs
. TXDx[7:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface, and passed to the encoder or Transmit
Shifter. When the Encoder is enabled, TXDx[7:0] specifies the specific data or
command character sent.
TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]
LVTTL Input,
synchronous,
sampled by the
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
Transmit Control
. TXCTx[1:0] inputs are captured on the rising edge of the transmit
interface clock. The transmit interface clock is selected by the TXCKSELx latch via
the device configuration interface, and passed to the Encoder or Transmit Shifter. The
TXCTA[1:0] inputs identify how the associated TXDx[7:0] characters are interpreted.
When the Encoder is bypassed, these inputs are interpreted as data bits. When the
Encoder is enabled, these inputs determine if the TXDx[7:0] character is encoded as
Data, a Special Character code, or replaced with other Special Character codes. See
Table 3
for details.
TXERRA
TXERRB
TXERRC
TXERRD
LVTTL Output,
synchronous to
REFCLKx
↑
[3]
,
synchronous to
RXCLKx when
selected as
REFCLKx,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of
REFCLKx±
Transmit Path Error
. TXERRx is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until either a Word Sync Sequence is transmitted on that channel, or the transmit
Phase-Align Buffer is re-centered with the PABRSTx latch via the device configuration
interface. When TXBISTx = 0, the BIST progress is presented on the associated
TXERRx output. The TXERRx signal pulses HIGH for one transmit-character clock
period to indicate a pass through the BIST sequence once every 511 or 527
(depending on RXCKSELx) character times. If RXCKSELx = 1, a one character pulse
occurs every 527 character times. If RXCKSELx = 0, a one character pulse occurs
every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
The TXPLL for the associated channel is powered down. This occurs when OE2x
and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.
The absence of the REFCLKx± signal
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
REFCLKC±
REFCLKD±
Differential LVPECL
or single-ended
LVTTL input clock
Reference Clock
. REFCLKx± clock inputs are used as the timing references for the
transmit and receive PLLs. These input clocks may also be selected to clock the
transmit and receive parallel interfaces. When driven by a single-ended LVCMOS or
LVTTL clock source, connect the clock source to either the true or complement
REFCLKx input, and leave the alternate REFCLKx input open (floating). When driven
by an LVPECL clock source, the clock must be a differential clock, using both inputs.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input,
internal pull-down
Transmit Path Input Clock
. When configuration latch TXCKSELx = 0, the associated
TXCLKx input is selected as the character-rate input clock for the TXDx[7:0] and
TXCTx[1:0] inputs. In this mode, the TXCLKx input must be frequency-coherent to its
associated TXCLKOx output clock, but may be offset in phase by any amount. Once
initialized, TXCLKx is allowed to drift in phase as much as ±180 degrees. If the input
phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer,
TXERRx is asserted to indicate the loss of data, and remains asserted until the Phase
Align Buffer is initialized. The phase of the TXCLKx input clock relative to its
associated REFCLKx± is initialized when the configuration latch PABRSTx is written
as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is initialized
and input characters are correctly captured.
Notes:
2.
3.
When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
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