- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYP15G0403DXB (Cypress Semiconductor Corp.) Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 12/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 12 of 43
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of the
TXCLKx relative to its associated internal character rate clock
is initialized when the configuration latch PABRSTx is written
as 0. When the associated TXERRx is deasserted, the Phase
Align Buffer is initialized and input characters are correctly
captured.
If the phase offset, between the initialized location of the input
clock and REFCLKx|, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRx output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
reset. While the error remains active, the transmitter for that
channel outputs a continuous C0.7 character to indicate to the
remote receiver that an error condition is present in the link.
Each Phase-Align Buffer may be individually reset with
minimal disruption of the serial data stream. When a Phase-
Align Buffer error is present, the transmission of a Word Sync
Sequence re-centers the Phase-Align Buffer and clears the
error indication.
Note
. K28.5 characters may be added or removed from the
data stream during the Phase Align Buffer reset operation.
When used with non-Cypress devices that require a complete
16-character Word Sync Sequence for proper receive
Elasticity Buffer Operation, it is recommend that the Phase
Alignment Buffer reset be followed by a Word Sync Sequence
to ensure proper operation.
Encoder
Each character received from the Input Register or Phase-
Align Buffer is passed to the Encoder logic. This block inter-
prets each character and any associated control bits, and
outputs a 10-bit transmission character.
Depending on the operational mode, the generated trans-
mission character may be
the 10-bit pre-encoded character accepted in the Input
Register.
the 10-bit equivalent of the 8-bit Data character accepted in
the Input Register.
the 10-bit equivalent of the 8-bit Special Character code
accepted in the Input Register.
Note:
7.
LSB shifted out first.
the 10-bit equivalent of the C0.7 violation character if a
Phase-Align Buffer overflow or underflow error is present.
a character that is part of the 511-character BIST sequence.
a K28.5 character generated as an individual character or
as part of the 16-character Word Sync Sequence.
Data Encoding
Raw data, as received directly from the Transmit Input
Register, is seldom in a form suitable for transmission across
a serial link. The characters must usually be processed or
transformed to guarantee
a minimum transition density (to allow the receive PLL to
extract a clock from the serial data stream).
a DC-balance in the signaling (to prevent baseline wander).
run-length limits in the serial data (to limit the bandwidth
requirements of the serial link).
the remote receiver a way of determining the correct
character boundaries (framing).
When the Encoder is enabled (ENCBYPx = 1), the characters
transmitted are converted from Data or Special Character
codes to 10-bit transmission characters, using an integrated
8B/10B encoder. When directed to encode the character as a
Special Character code, the encoder uses the Special
Character encoding rules listed in
Table 16
. When directed to
encode the character as a Data character, it is encoded using
the Data Character encoding rules in
Table 15
.
The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 Fibre Channel, IEEE 802.3z Gigabit
Ethernet, the IBM
ESCON
and FICON channels, ETSI
DVB-ASI, and ATM Forum standards for data transport.
Many of the Special Character codes listed in
Table 16
may be
generated by more than one input character. The
CYP(V)(W)15G0403DXB is designed to support two
independent (but non-overlapping) Special Character code
tables. This allows the CYP(V)(W)15G0403DXB to operate in
mixed environments with other Cypress HOTLink devices
using the enhanced Cypress command code set, and the
reduced command sets of other non-Cypress devices. Even
when used in an environment that normally uses non-Cypress
Special Character codes, the selective use of Cypress
command codes can permit operation where running disparity
and error handling must be managed.
Following conversion of each input character from eight bits to
a 10-bit transmission character, it is passed to the Transmit
Shifter and is shifted out LSB first, as required by ANSI and
IEEE standards for 8B/10B coded serial data streams.
Transmit Modes
Encoder Bypass
When the Encoder is bypassed, the character captured from
the TXDx[7:0] and TXCTx[1:0] input register is passed directly
to the transmit shifter without modification. With the encoder
bypassed, the TXCTx[1:0] inputs are considered part of the
data character and do not perform a control function that would
otherwise modify the interpretation of the TXDx[7:0] bits. The
bit usage and mapping of these control bits when the Encoder
is bypassed is shown in
Table 2
.
Table 1. Input Register Bit Assignments
[7]
Signal Name
TXDx[0] (LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1] (MSB)
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
Encoded
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
相關PDF資料 |
PDF描述 |
|---|---|
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYRF69103 | Programmable Radio on Chip Low Power |
| CYRF69213 | Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | Programmable Radio on Chip Low Power |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep Channel XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。