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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 16/43頁 |
| 文件大小： | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 16 of 43
with a half-character-rate output clock, the output of properly
framed characters may be delayed by up to 14 character-clock
cycles from the detection of the framing character.
Note
.
When Receive BIST is enabled on a channel, the Low-
Latency Framer must not be enabled. The BIST sequence
contains an aliased K28.5 framing character, which causes the
Receiver to update its character boundaries incorrectly.
When RFMODEx[1:0] = 10, the Cypress-Mode Multi-Byte
framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased SYNC characters in the data
stream. In this mode, the framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock does not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode the character boundaries are only
adjusted if the selected framing character is detected at least
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
When RFMODEx[1:0] = 01, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the data stream
must contain a minimum of four of the selected framing
characters, received as consecutive characters, on identical
10-bit boundaries, before character framing is adjusted.
10B/8B Decoder Block
The decoder logic block performs two primary functions:
decoding the received transmission characters to Data and
Special Character codes
comparing generated BIST patterns with received
characters to permit at-speed link and device testing.
The framed parallel output of each deserializer shifter is
passed to its associated 10B/8B Decoder where, if the
decoder is enabled, the input data is transformed from a 10-bit
transmission character back to the original Data or Special
Character code. This block uses the 10B/8B decoder patterns
in
Table 15
and
Table 16.
Received Special Code characters
are decoded using
Table 16
. Valid data characters are
indicated by a 000b bit-combination on the associated
RXSTx[2:0] status bits, and Special Character codes are
indicated by a 001b bit-combination of these status outputs.
Framing characters, Invalid patterns, disparity errors, and
synchronization status are presented as alternate combina-
tions of these status bits.
When DECBYPx = 0, the 10B/8B decoder is bypassed via the
configuration interface. When bypassed, raw 10-bit characters
are passed through the receiver and presented at the
RXDx[7:0] and the RXSTA[1:0] outputs as 10-bit wide
characters.
When the decoder is enabled by setting DECBYPx = 1 via the
configuration interface, the 10-bit transmission characters are
decoded using
Table 15
and
Table 16
. Received Special
characters are decoded using
Table 16
. The columns used in
Table 16
are determined by the DECMODEx latch via the
device configuration interface. When DECMODEx = 0 the
ALTERNATE table is used and when DECMODEx = 1 the
CYPRESS table is used.
Receive BIST Operation
The receiver channel contains an internal pattern checker that
can be used to validate both device and link operation. These
pattern checkers are enabled by the associated RXBISTx
latch via the device configuration interface. When enabled, a
register in the associated receive channel becomes a
signature pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character or 526-character sequence
that includes all Data and Special Character codes, including
the explicit violation symbols. This provides a predictable yet
pseudo-random sequence that can be matched to an identical
LFSR in the attached Transmitter(s). When synchronized with
the received data stream, the associated Receiver checks
each character in the Decoder with each character generated
by the LFSR and indicates compare errors and BIST status at
the RXSTx[2:0] bits of the Output Register.
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0. This code D0.0 is sent only once per BIST loop. The
status of the BIST progress and any character mismatches are
presented on the RXSTx[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period
per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. These same status values
are presented when the decoder is bypassed and BIST is
enabled on a receive channel.
The specific status reported by the BIST state machine are
listed in
Table 11
. These same codes are reported on the
receive status outputs.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In Self-
Test.”
The
sequence
CYP(V)(W)15G0403DXB is identical to that in the CY7B933,
CY7C924DX, and CYP(V)(W)15G0401DXB, allowing interop-
erable systems to be built when used at compatible serial
signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to the D0.0 state to look for the start of the BIST sequence
again.
When the receive paths are configured for REFCLKx±
operation, each pass must be preceded by a 16-character
Word Sync Sequence to allow management of clock
frequency variations.
The receive BIST state machine requires the characters to be
correctly framed for it to detect the BIST sequence. If the Low
Latency Framer is enabled, the Framer misaligns to an aliased
SYNC character within the BIST sequence. If the Alternate
Multi-Byte Framer is enabled and the Receiver outputs are
clocked relative to a recovered clock, it is generally necessary
to frame the receiver before BIST is enabled. If the receive
outputs are clocked relative to REFCLKx±, the transmitter
precedes every 511 character BIST sequence with a 16
character-character Word Sync Sequence.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
compared
by
the
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