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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 15 of 43
input. If the VCO is running at a frequency beyond
±1500 ppm
[30]
as defined by the REFCLKx± frequency, it is
periodically forced to the correct frequency (as defined by
REFCLKx±, SPDSELx, and TXRATEx) and then released in
an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track REFCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP(V)(W)15G0403DXB contains four receive channels
that can be independently enabled and disabled. Each
channel can be enabled or disabled separately through the
RXPLLPDx input latch as controlled by the device configu-
ration interface. When the RXPLLPDx latch = 0, the
associated PLL and analog circuitry of the channel is disabled.
Any disabled channel indicates a constant link fault condition
on the LFIx output. When RXPLLPDx = 1, the associated PLL
and receive channel is enabled to receive and decode a serial
stream.
Note
. When a disabled receive channel is reenabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate for
up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and align the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate
÷
10) or half-
character-rate (bit-rate
÷
20) reference clock from the
associated REFCLKx± input. This REFCLKx± input is used to
ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit-rate)
reduce PLL acquisition time
limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks REFCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns back close to REFCLKx± frequency, the CDR input is
switched back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may result
in brief RXCLK± frequency excursions from REFCLKx±.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of REFCLKx± is required to be
within ±1500 ppm
[30]
of the frequency of the clock that drives
the REFCLKx± input of the
remote
transmitter to ensure a lock
to the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream and frame to the incoming character bound-
aries.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the bit-
clock rate. When enabled, the Framer examines the data
stream looking for one or more COMMA or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Framing Character
The CYP(V)(W)15G0403DXB allows selection of different
framing characters on each channel. Two combinations of
framing characters are supported to meet the requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHARx latches via the configuration
interface.
The specific bit combinations of these framing characters are
listed in
Table 6
. When the specific bit combination of the
selected framing character is detected by the framer, the
boundaries of the characters present in the received data
stream are known.
Table 6. Framing Character Selector
Framer
The framer on each channel operates in one of three different
modes. Each framer may be enabled or disabled using the
RFENx latches via the configuration interface. When the
framer is disabled (RFENx = 0), no combination of received
bits alters the frame information.
When the Low-Latency framer is selected (RFMODEx[1:0] =
00), the framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode the framer starts its alignment process on the first
detection of the selected framing character. To reduce the
impact on external circuits that use the recovered clock, the
clock period is not stretched by more than two bit-periods in
any one clock cycle. When operated with a character-rate
output clock, the output of properly framed characters may be
delayed by up to nine character-clock cycles from the
detection of the selected framing character. When operated
FRAMCHARx
0
Bits detected in framer
Character Name
COMMA+
COMMA–
–K28.5
+K28.5
Bits Detected
00111110XX
[9]
or 11000001XX
0011111010 or
1100000101
1
Note:
9.
The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
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