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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| 中文描述： | 獨立時鐘四路HOTLink II收發(fā)器（獨立時鐘，四熱連接二收發(fā)器） |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 744K |
| 代理商： | CYP15G0403DXB |
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CYV15G0403DXB
CYW15G0403DXB
CYP15G0403DXB
Document #: 38-02065 Rev. *E
Page 18 of 43
When the low-latency framer and half-rate receive port
clocking are also enabled, the framer stretches the recovered
clock to the nearest 20-bit boundary such that the rising edge
of RXCLKx+ occurs when COMDETx is present on the
associated output bus.
When the Cypress or Alternate Mode Framer is enabled and
half-rate receive port clocking is also enabled, the output clock
is not modified when framing is detected, but a single pipeline
stage may be added or subtracted from the data stream by the
framer logic such that the rising edge of RXCLKx+ occurs
when COMDETx is present on the associated output bus.
This adjustment only occurs when the framer is enabled.
When the framer is disabled, the clock boundaries are not
adjusted, and COMDETx may be asserted during the rising
edge of RXCLKx– (if an odd number of characters were
received following the initial framing).
Receive Status Bits
When the 10B/8B decoder is enabled, each character
presented at the Output Register includes three associated
status bits. These bits are used to identify
if the contents of the data bus are valid,
the type of character present,
the state of receive BIST operations,
character violations.
These conditions often overlap; e.g. a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a decoder
violation of some specific type. This implies a hierarchy or
priority level to the various status bit combinations. The
hierarchy and value of each status are listed in
Table 11
.
A second status mapping, listed in
Table 11
, is used when the
receive channel is configured for BIST operation. This status
is used to report receive BIST status and progress.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0]
bits identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in
Figure 2
and
Table 11
. When the receive PLL detects an out-
of-lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state
machine. If the number of detected errors ever exceeds the
number of valid matches by greater than 16, the state machine
is forced to the WAIT_FOR_BIST state where it monitors the
receive path for the first character of the next BIST sequence
(D0.0). Also, if the Elasticity Buffer ever hits an
overflow/underflow condition, the status is forced to the
BIST_START until the buffer is re-centered (approximately
nine character periods).
To ensure compatibility between the source and destination
systems when operating in BIST modes, the sending and
receiving ends of the link must use the same receive clock
configuration.
Device Configuration and Control Interface
The CYP(V)(W)15G0403DXB is highly configurable via the
configuration interface. The configuration interface allows the
device to be configured globally or allows each channel to be
configured independently.
Table 9
lists the configuration
latches within the device including the initialization value of the
latches upon the assertion of RESET.
Table 10
shows how the
latches are mapped in the device. Each row in the
Table 10
maps to a 8-bit latch bank. There are 16 such write-only latch
banks. When WREN = 0, the logic value in the DATA[7:0] is
latched to the latch bank specified by the values in ADDR[3:0].
The second column of
Table 10
specifies the channels
associated with the corresponding latch bank. For example,
the first three latch banks (0,1 and 2) consist of configuration
bits for channel A. The latch banks 12, 13 and 14 consist of
Global configuration bits and the last latch bank (15) is the
Mask latch bank that can be configured to perform bit-by-bit
configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can be used to reduce the number of write opera-
tions needed to setup the latch banks. This function is
beneficial in systems that use a common configuration in
multiple channels. The GLENx bit is present in bit 0 of latch
banks 0 through 11 only. Its default value (1) enables the global
update of the latch bank's contents. Setting the GLENx bit to
0 disables this functionality.
Latch Banks 12, 13, and 14 are used to load values in the
related latch banks in a global manner. A write operation to
latch bank 12 could do a global write to latch banks 0, 3, 6, and
9 depending on the value of GLENx in these latch banks; latch
bank 13 could do a global write to latch banks 1, 4, 7 and 10;
and latch banks 14 could do a global write to latch banks 2, 5,
8 and 11. The GLENx bit cannot be modified by a global write
operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is used as a global mask vector
to control the update of the configuration latch banks on a bit-
by-bit basis. A logic 1 in a bit location allows for the update of
that same location of the target latch bank(s), whereas a logic
0 disables it. The reset value of this latch bank is FFh, thereby
making its use optional by default. The mask latch bank is not
maskable. The FGLEN functionality is not affected by the bit 0
value of the mask latch bank.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change dynamically during the appli-
cation's lifetime.The first row of latches for each channel
(address numbers 0, 3, 7, and 10) are the static receiver
control latches. The second row of latches for each channel
(address numbers 1, 4, 8, and 11) are the static transmitter
control latches. The third row of latches for each channel
(address numbers 2, 5, 9, and 12) are the dynamic control
latches that are associated with enabling dynamic functions
within the device.
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| CYP15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep Channel XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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