參數(shù)資料
型號： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁數(shù)： 96/99頁
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
10.0 Register Definition
Table 118 below contains the address for all of the internal registers. Once the EE has been written, the POR states for the registers
become the data last written. Should the CheckSum fail, all registers will return to the POR state shown, and an error flag will be
written to a status register.
Table 118: Register List
Address
R/W
Hex
Dec
R/W
0x00
0
Command
Instruction register
R/W
0x01
1
Status1
Part status, flags
R/W
0x02
2
Status2
Part status, flags
R/W
0x03
3
Chip Address 1
Upper 8 bits of chip address
R/W
Chip Address 0
0x04
4
Lower 8 bits of chip address
R/W
0x05
5
RF Divider
Integer portion of RF frequency
R/W
0x06
6
Upper 8 bits of RF fraction
RF Frequency 2
R/W
0x07
7
RF Frequency 1
Center 8 bits of RF fraction
R/W
0x08
8
RF Frequency 0
Lower 8 bits of RF fraction
R/W
0x09
9
Peak Deviation 1
Upper 8 bits of FM deviation
R/W
0X0A
10
Peak Deviation 0
Lower 8 bits of FM deviation
R/W
0x0B
11
Data Rate / Format
Set discrete data rate and encoding option
General options for interface, POR state,
etc.
General options for interface, POR state,
etc.
R/W
0x0E
14
RX Config
Receiver options
R/W
0x0F
15
TX Config
Transmit options
R/W
0x10
Idle mode options
16
Idle Config
R/W
0x11
17
Sniff Config
Sniff Mode options
R/W
0x12
18
Sniff Interval
Interval between Sniff cycles
R/W
0x13
19
Energy Dwell Time
Length of time to dwell in Sniff Mode
Number of bit times to wait for code
0x14
Code Dwell Timer
Register Name
Description
POR State
EE
Section
X
X
X
X
X
X
X
X
X
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
6.2
6.4.5.1
6.4.5.2
7.1.1
7.1.2
6.4.1.1
6.4.1.2
6.4.1.3
6.4.1.4
6.4.1.5
6.4.1.6
7.1.3
R/W
General Options A
X
0x0C
12
0000_0000
7.1.4
R/W
0x0D
13
General Options B
0000_0000
X
7.1.5
0000_0000
0000_0000
1011_0100
0000_1010
0000_0000
X
X
X
X
X
X
6.5.1.1
6.6.1
6.7.1
6.7.2.1
6.7.2.2
6.7.2.3
R/W
20
after energy
Threshold for wake on RSSI, Sniff
and CCA
Burst transmit options
Interval timer for burst transmit
Output power
Byte used for burst transmit/CDR wake up
Length of CW, or ‘10’
repeated in Burst/TX (BT’s)
Housekeeping options register
Interval timer for housekeeping
Energy threshold for AM DAC mode
data slice
AM/RSSI filter setting and AM slice mode
Clock and data recovery options A
Clock and data recovery options B
Crystal trim
LNA input and output matching trim
Quick Start oscillator trim
6.5.1.5
0000_0000
X
R/W
0x15
21
Energy Threshold
0000_0000
X
6.5.1.2
R/W
R/W
R/W
R/W
0x16
0x17
0x18
0x19
22
23
24
25
Burst Config
Burst Interval
Output Power
Start of Frame
0000_0000
0001_1000
0001_0000
0001_0000
X
X
X
X
6.7.3
6.7.3.1
6.6.2
7.1.6
R/W
0x1A
26
Preamble Length
0001_0000
X
6.6.3
R/W
R/W
0x1B
0x1C
27
28
HK Config
HK Interval
X
X
6.7.4.1
6.7.4.2
R/W
0x1D
29
Slice Threshold
X
6.5.1.4
R/W
R/W
R/W
R/W
R/W
R/W
0x1E
0x1F
0x20
0x21
0x22
0x23
30
31
32
33
34
35
Filter/Slice
CDR Options A
CDR Options B
Crystal Trim
LNA Trim
Quick Start Trim
1000_0000
0000_0000
0000_0000
0000_0000
X
X
X
X
X
X
6.5.1.4
6.5.1.5
6.5.1.5
6.10.1.1
6.10.1.2
6.10.1.3
96
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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