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參數資料
| 型號： | AMIS-53000-M |
| 英文描述： | Frequency Agile Transceiver |
| 中文描述： | 捷變頻收發(fā)器 |
| 文件頁數： | 88/99頁 |
| 文件大小： | 2638K |
| 代理商： | AMIS-53000-M |
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AMIS-53000
Frequency Agile Transceiver
Data Sheet
Figure 49: Data Interface Protocol (ID and LOP)
7.2.9.3.
Use ID Enabled, CRC Enabled, LOP Enabled
Table 107: Receive
Parameter
ID
CRC
LOP
CRC
Invalid
CRC Valid
Table 108: Transmit
Parameter
Action
Data interface immediately ready after ID detected
As soon as the ID is validated, the CRC starts processing the data
The LOP is received
The rest of the received data packet is buffered into memory
The last byte is the CRC and if invalid, the receiver waits for a command from the external host/controller, or if the receiver
came from idle it will return to receive
Receiver returns to previous state and an interrupt is issued to the external controller
The data interface is started and the data is sent to the controller, except for the CRC
Action
If buffered transmit is selected, the AMIS-53000 will open the data interface and transfer all TX data into memory with
AMIS-53000 as master or external controller as master
Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transmits preamble (length of preamble as specified)
Transmits the SOF and the ID
The CRC begins processing the data with the ID
Starts data interface and uses a synchronous clock to clock in the TX data (master only)
or clocks data out of memory (buffered TX)
The first byte is defined to be the LOP of the packet
At the end of the packet, the data stops and the CRC value is sent
After the packet is transmitted, the transmitter waits for a command from the external host/controller
Buffered Transmit
Transmit
ID
CRC
LOP
CRC Byte
88
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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