參數(shù)資料
型號(hào)： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁(yè)數(shù)： 56/99頁(yè)
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
CDR Options A
This register contains settings for determining the clock and data recovery parameters.
DR_Clamp: Limits the CDR frequency drift between data packets.
Channel_Clamp: Restricts the bandwidth to the channel bandwidth.
Activity Check: Sets a number of bit times that the CDR circuit will shut down if there is no data present.
Fast Phase Alignment: Forces the CDR circuit to quickly synchronize to the incoming data.
FM Mode: The FM detector used in the receiver depends on the data rate of the incoming signal.
Table 41: CDR OptionsA - 0X1F [31]
Bit
Name
State
Comment
1/64
1/32
1/16
01
00
1/8
11
+-150
10
+-100
01
+-50
00
+-16
11
10
01
00
Activity check disabled, clock recovery will always run
1
The CDR circuit will perform fast phase alignment
1
FPA Enable
0
CDR always running
1
PLL
0
FM Mode
0
FFT
7,6
DR Clamp<1>
11
10
The clamp restricts the clock recovery PLL to +- the fraction selected
of the frequency selected by the BaudCLK which prevents clock
wandering between data packets
5,4
Channel Clamp
The clamp restricts the PLL detector to only lock on signals that are
within the specified window, centered +-500kHz of the IF frequency
3,2
Activity Check <1>
Reset after 16 bit times of no activity
Reset after 8 bit times of no activity
Reset after 4 bit times of no activity
CDR Options B
The sample clock values are written from ROM with the discrete data rate selected. The sample rate should be as fast as possible
without exceeding 400 samples per bit time.
Table 42: CDR OptionsB - 0X20 [32]
Bit
Name
State
Comment
1
CDR is held reset
7
CDR Reset
0
6
NU
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
24M
5
NU
4
NU
3:0
Sample Clock
45kHz
90kHz
187.5kHz
375kHz
750kHz
1.5M
3M
6M
8M
12M
16M
56
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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