參數(shù)資料
型號(hào)： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁(yè)數(shù)： 83/99頁(yè)
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
Table 97: TX/RX Data Protocols
Modulation
Detector
CDR
Opt
1
Preamble
SOF
Yes
2
ID/LOP/CRC
Slice
AM
RSSI
CW
See Table 98
Fixed/Auto
FM (<20kbps)
PLL
Yes
1 0 pattern
-------
See Table 98
-------------
FM (>20kbps)
FFT
Yes
3
4
See Table 98
-------------
Notes:
1. The use of the CDR function to recover the data is recommended for AM/OOK modulation.
2. The SOF for AM modulation is suggested to be 55 (HEX) for NRZ and 0A (HEX) for Manchester encoded data.
3. The preamble for FM (FFT) with NRZ data is a 1 0 repeating pattern. The preamble for FM (FFT) with Manchester encoded data is all 1s or all 0s.
4. A SOF is only required for FM (FFT) when the data is Manchester encoded. The suggested SOF is a pattern of 55 (HEX) or AA (HEX).
Table 98: Interface Data Protocols
TX/RX Data Protocol
Interface Data
Protocol
Comments
LOP
CRC
Interface
Data
Stream
1
N
N
Active
Data is streamed out the interface as it is received
N
N
Active*
Stream
* Data is streamed out the interface starting with the wakeup on ID
Y
N
Interrupt
Buffered
An interrupt is issued when data reception is complete
Y
Y
Interrupt
Buffered
An interrupt is issued when data reception is complete
Notes:
1. When the interface uses streaming data, the AMIS-53000 must be the master.
The serial data interface for the AMIS-53000 can be configured to be a 3-wire interface or a 4-wire SPI interface. The AMIS-53000 can
be configured to act as a master or a slave for both receive and transmit operation. Bit 2 in the general options B register allows the
user to select whether DATA will be sampled on the rising, or falling edge of DCLK. The setting for the sampling polarity applies to all
modes.
Table 99: Serial Data Interface Configuration
General Options B
Data Port Configuration
Pin Function Definition
Bit 7
Bit 6
Bit 2
# Port
Pins
AMIS-53000
Edge
Sample
DCLK
DSSN
DRXTX
DOPT
0
0
X
3
Master
X
Output
Output
I/O
X
0
1
X
3
Slave
X
Input
Input
I/O
X
1
0
X
4
Master
X
Output
Output
Output
Input
1
1
X
4
Slave
X
Input
Input
Output
Input
X
X
0
X
X
Falling
X
X
1
X
X
Rising
7.2.1. AMIS-53000 in Master Mode
In receive mode, the DSSN pin will transition low when the AMIS-53000 has received data. Immediately following the transition of
DSSN, the AMIS-53000 will provide a synchronized bit clock on DCLK, and the received data will appear on DRXTX.
In transmit mode, the transition of DSSN is used to signal an external host/controller that the AMIS-53000 is ready for transmit data and
is ready to receive that data on the DRXTX pin. Immediately following the transition of DSSN, the AMIS-53000 will provide a
synchronous clock on DCLK for the host/controller to use for loading transmit data into the AMIS-53000.
83
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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