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參數(shù)資料
| 型號： | AMIS-53000-M |
| 英文描述： | Frequency Agile Transceiver |
| 中文描述： | 捷變頻收發(fā)器 |
| 文件頁數(shù)： | 41/99頁 |
| 文件大?。?/td> | 2638K |
| 代理商： | AMIS-53000-M |
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AMIS-53000
Frequency Agile Transceiver
Data Sheet
Setup registers descriptions:
RF Divider
- The RF frequency of the receiver must be configured. This is done in two steps, one is setting the RF divider and
the other is setting the fractional N word.
RF Frequency
- Program the 3 register fractional N word.
Peak Deviation
- When the data modulation is to be FSK, the 2 register peak deviation must also be set. The deviation should
be set to a value between and 1 times the data rate.
PLL
- Configure the parameters for the PLL.
Loop Filter
- Configure the parameters for the loop filter.
6.4.1.1.
RF Divider
Setting the RF channel frequency is done through the RF divider register, along with the RF frequency 2, 1 and 0 registers. The RF
divider register is used to specify the integer portion of the divide value, and the RF frequency 2, 1 and 0 registers are used to specify
the fraction. The values are calculated as follows:
Where F
Channel
is the desired RF center frequency. The value for the RF divider register is found by,
Where integer is the value used for RF divider. The last step is to calculate the fractional value. This is done as,
raction is the value to be used in the RF frequency 2, 1 and 0 registers. As an example, if the desired RF frequency channel is
903.5MHz,
F
For this example, the RF di
frequency 0 to 0x54.This valu
Table 18: RF Divider - 0X05 [5]
Bit
Name
vider register is written to 0x26, RF frequency 2 is written to 0xFE, RF frequency 1 to 0x95, and RF
e +
y to the PLL as N0 and N1. (i.e. if 63, send 64 and 65 to the PLL)
/- 1 is fed directl
Comment
00h through 0Bh: not allow
1Ah: divide by 26
1Bh: divide by 27
-----------
4Ah: divide by 74
7:0
RF_divide [7:0]
ed
4Bh: divide by 75
4Ch through FFh: not allowed
41
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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