參數(shù)資料
型號(hào)： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁數(shù)： 77/99頁
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
7.1.1. Chip Address MSB1
The 16 bit ID that can be used for several purposes in the AMIS-53000 is stored in the chip address MSB, and chip address LSB
registers.
Table 85: Chip Address1 - 0X03 [3]
Bit
Name
Comment
7:0
Chip_Add [15:8]
Upper byte of chip address
7.1.2. Chip Address LSB
Table 86: Chip Address0 - 0X04 [4]
Bit
Name
7:0
Chip_Add [7:0]
Comment
Lower byte of chip address
7.1.3. Data Rate/Format
The data rate/format register is used to select the data rate and format for both receive and transmit. The DDRATE[2:0} option bits
allow selection of one of eight pre-programmed data rates. When one of the discrete data rates is selected, the ROM2REGS command
is used to load clock and data recovery settings for the desired data rate into their associated registers.
The Manchester option bit configures the AMIS-53000 to transmit and receive in the Manchester encoded format, while the data
interface remains NRZ.
If a data rate other than one of the available discrete rates is desired, the user should set the use custom bit, and then program the
custom data rate register for the desired data rate. When the use custom data rate option is enabled, it is up to the user to set the
correct sample clock frequency in the CDR options B register, set clock recovery loop filter settings, and if using the PLL based FSK
detector, set the PLL detector loop filter.
Note: For data rates that are near one of the pre-defined data rates, a discrete data rate could first be chosen, the ROM2REGS
command given to load all of the settings for the various blocks for that data rate, and then the custom data rate option enabled and the
new data rate information entered.
For example, if the desired data rate is 100kbps, set DDRATE to 110 for 96kbps operation. Next, issue the ROM2REGS command in
the command register. All of the proper settings for the clock and data recovery circuit for a 96k data rate will be loaded into the
working registers from ROM (sample clock frequency, clock recovery loop filter settings). Finally, enable the use custom option, and
program data rate 1, and 0 with the value for a 100k data rate.
Custom frequency is set in data rate 1 and data rate 0. If custom is 0, ROM contents for selected discrete data rate are loaded into
data rate 1 and data rate 0.
77
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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