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參數(shù)資料
| 型號： | AMIS-53000-M |
| 英文描述： | Frequency Agile Transceiver |
| 中文描述： | 捷變頻收發(fā)器 |
| 文件頁數(shù)： | 30/99頁 |
| 文件大?。?/td> | 2638K |
| 代理商： | AMIS-53000-M |
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AMIS-53000
Frequency Agile Transceiver
Data Sheet
External controller can read registers
External controller can issue a immediate transmit via the xBURST input
External controller can receive an interrupt (xINT) from the AMIS-53000
Setup registers descriptions:
I
2
C/3-wire select
- First write to the interface sets the type of interface until AMIS-53000 is power cycled.
6.1.2. Serial Control Interface: Configuration
The AMIS-53000 can automatically detect the type of interface for the serial control bus. The interface pins are then given the
definitions as shown in Table 14. The detection depends on the status of the AMIS-53000 pins as shown in Figure 23.
Table 14: Control Port Pin Definitions
I
2
C Mode
3-Wire Mode
Pin Name
SCLK
SCL
SCLK
SDATA
SDA
R/W controlled
SSN
Internal pull up
SSN
Figure 23: Control Interface Selection
Simply addres
selection is loc
ws:
as follo
the desired pro
rface selection. After the first communication with the part, the
the device. The internal logic for determining which protocol to use on initial power up is
I
2
C:
If SSN is high and an I
2
C start bit is detected, I
2
C mode is enabled.
3-wire:
If SSN is low, and a negative edge on SCLK detected, 3-wire mode is enabled.
The internal pull ups on SCLK and SDATA can also be disabled for I
2
C applications using external pull ups.
Table 15: Control Interface Pull Up Control
sing the part with
ked until power is removed from
tocol performs initial inte
Mode
SCLK, SDATA Pull Ups
SSN Pin Configuration
I
2
C
Controlled by bit 3 of the general
options A register
Not used (internal pull up)
3-wire
Controlled by bit 3 of the general
options A register
SSN: normal mode
30
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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