參數(shù)資料
型號(hào)： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁(yè)數(shù)： 33/99頁(yè)
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
6.1.4.1.
I2C Device Addressing
A control byte is the first byte received following the start condition from the master device. The control byte consists of a 7-bits for the
device address, and 1-bit for a read or write command. For the AMIS-53000, the device address is ‘0110100’ binary. The last bit of the
control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is
selected. Following the start condition, the AMIS-53000 monitors the SDA bus checking the device type identifier being transmitted.
Upon receiving its device address, the AMIS-53000 outputs an acknowledge signal on the SDA line. Depending on the state of the R/W
bit, the AMIS-53000 will select a read or write operation.
6.1.4.2.
Single Register Write
Figure 27: Single Control Data Read/Write with the I
2
C Interface
The master device issues the start condition, then issues the device address, and then issues the single R/W bit, a logic low state. This
indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit
during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be written with data. After
receiving another acknowledge signal from the AMIS-53000, the master device will transmit the data word to be written, and the
AMIS-53000 will acknowledge again. The write cycle ends with the master generating a stop condition.
A similar approach is used to read a register value. The master device issues the start condition, then issues the device address, and
then issues the single R/W bit, a logic low state. This indicates to the addressed slave receiver that a byte with a register address will
follow after the slave has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master
is the register address to be read. After receiving another acknowledge signal from the AMIS-53000, the master device will immediately
follow with another start sequence, however, the R/W bit is now set high telling the slave device that the master wants the contents of
the register (addressed with the write command) to be placed on the SDA bus line. After 8 bits of data are read by the master, the
master does not acknowledge but sends the stop sequence.
33
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
相關(guān)PDF資料
PDF描述
AMIS-53050 Frequency Agile Transceiver
AMIS-710650 Color CIS Module Analog Video Output
AMIS-710650-A6 Color CIS Module Analog Video Output
AMIS-710651 Color CIS Module
AMIS-710651-A4 Color CIS Module
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AMIS-53050 制造商:ON Semiconductor 功能描述:WIRELESS LOW POWER TRANSC - 300-960MHZ, XTRA LOW RX PW, LQFP - Trays 制造商:ON Semiconductor 功能描述:WIRELESS LOW POWER TRANSC - 300-960MHZ, XTRA LOW RX PW, LQFP - Tape and Reel 制造商:ON Semiconductor 功能描述:WIRELESS LP TRANSC - 300-960MHZ, SPI INTERFACE:GANG XC, LQFP - Trays 制造商:ON Semiconductor 功能描述:WIRELESS LP TRANSC - 300-960MHZ, SPI INTERFACE:GANG XC, LQFP - Tape and Reel
AMIS-53050-I/A 制造商:AMI 制造商全稱(chēng):AMI 功能描述:Frequency Agile Transceiver
AMIS-53050-XTD 功能描述:射頻收發(fā)器 AMIS-53050 WLESS TRNSCVR RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類(lèi)型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類(lèi)型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
AMIS-70020 制造商:ON Semiconductor 功能描述:POWER FAILURE ELAPSED TIME COUNTER, SOIC - Rail/Tube 制造商:ON Semiconductor 功能描述:POWER FAILURE ELAPSED TIME COUNTER, SOIC - Tape and Reel
AMIS-710200 制造商:AMI 制造商全稱(chēng):AMI 功能描述:200dpi CIS Module
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*