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參數(shù)資料
| 型號： | AMIS-53000-M |
| 英文描述： | Frequency Agile Transceiver |
| 中文描述： | 捷變頻收發(fā)器 |
| 文件頁數(shù)： | 59/99頁 |
| 文件大小： | 2638K |
| 代理商： | AMIS-53000-M |
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AMIS-53000
Frequency Agile Transceiver
Data Sheet
6.6.2. Output Power
C_POWER:
Coarse output power control for the power amplifier. When set high, the max out is 15dBm - when set low, the
max output is 0dBm.
F_POWER:
Fine output power control for the PA. These 7 bits control the voltage on the RFPWR pin via an internal
DAC.F_POWER is sent to the DAC as the upper 6 bits. Lower 2 bits are 0.
Table 46: Output Power - 0X18 [24]
Bit
Name
7
C_POWER
6:0
F_POWER [6:0]
Comment
Coarse output power selection sent to PA
Fine output power control (upper 7 bits of the DAC, LSB of DAC=0)
6.6.3. Preamble Length
This byte is used to define the length of preamble to send prior to data in both transmit and Burst mode transmit.
Table 47: Preamble Length - 0X1A [26]
Bit
Name
Comment
7
PreambleLen [7:0]
Length, in bit times, of CW (AM), or ’10 (FM) sent prior to preamble in Burst
Table 48: Suggested Preambles
Modulation
Preamble
Comment
AM NRZ with CDR
CW
AM Manchester with CDR
CW
FM FFT
1/0 pattern
No SOF is required
FM PLL
(NRZ)
FM PLL (Manchester)
All 1s or 0s
Notes:
1. When using SOF with NRZ data, it is suggested that fast phase alignment is enabled, activity check is set to 8 or 16 and preamble length is 10 or 20 bit times.
2. When using SOF with Manchester coded data, it is suggested that fast phase alignment is enabled, activity check is set to 4 bit times and preamble length is set long
enough to trigger the activity check.
3. The length of this preamble is dependent on the loop bandwidth of the recovery clock PLL.
SOF required and suggested as 0X55
1
SOF required and suggested as 0x0A
2
1/0 pattern
No SOF is required
SOF is required and suggested to be 55(Hex) or AA(Hex)
3
6.6.4. FM Transmit Data Shaping
The AMIS-53000 allows the user to enable data shaping of the data waveform to improve the RF spectral efficiency. When enabled,
the clock recovery NCO is used to provide an internal clock at 16 times the selected data rate. This clock is used to cycle through a
pre-defined pattern whenever a transition is detected on the TX input. The shaping pattern is Gaussian with a BT=1. The intermediate
values for the shaping are determined from the peak deviation register when an external host/controller writes the ‘ROM 2 REGS’ to the
AMIS-53000 command register.
59
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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