參數(shù)資料
型號(hào)： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁(yè)數(shù)： 66/99頁(yè)
文件大小： 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
Used to set the options for the Burst mode of operation:
R_BURST:
These bits set the number of times the packet is to be repeated each Burst interval. This can be used to increase
the probability that all packets will get through when several Burst transmitters are located in the same area.
Send Chip ID:
This option is included to allow for the operating case of having multiple transmitters sending to a single
receiver. The multiple transmitters will need to be configured to send the global chip ID in the TX config options so that the
receiver will wake on each transmitters packet. Sending the chip ID as part of the payload allows the receiver to differentiate
the packets.
Send Internal ADC Data:
When enabled, the AMIS-53000 will perform conversions on the battery voltage, and temperature
sensor and include these conversions as part of the packet payload.
Send External ADC Data:
When enabled, the AMIS-53000 will perform conversions on the two external ADC inputs and
include these conversions as part of the packet payload.
Burst Interval Resolution:
Used to define the clock frequency for the Burst interval timer.
Table 60: Burst Config - 0X16 [22]
Bit
Name
State
Comment
1
7
0
1
6
0
00
01
10
11
Packet is repeated three times
1
Chip ID is included as part of the packet
3
Send Chip ID
0
1
Data for temperature and battery is sent
2
ADC Data
0
1
Data for EXT1, EXT2 is sent
1
ADC Data
0
1
Burst interval timer resolution is 15s
0
Resolution
0
Burst interval timer resolution is 50ms
NOTE: When the Burst transmission is repeated the interval between transmissions is a random time period produced in a random number generator with the chip ID value
used to seed the random number generator.
5:4
R_BURST[1:0]
Packet is sent one time
Packet is repeated once
Packet is repeated two times
Repeat interval*
Send Internal
Send External
Burst Interval
6.7.3.1.
Burst Interval
Defines the period for the normal Burst transmission to occur. This is a cyclic mode and the AMIS-53000 will transmit the contents of a
register at the end of each interval. This interval is fixed by the register value unlike the random time interval when the transmission is
repeated.
Table 61: Burst Interval - 0X17 [23]
Bit
Name
Comment
7:0
BURST_INT [7:0]
Burst interval= (BURST_INT+1)*Burst interval resolution
66
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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