參數(shù)資料
型號： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁數(shù)： 13/99頁
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
Table
Pin#
17
18
19
20
21
7: Pin D
efinitions (Continued)
-001
Drxtx
Dclk
SYSclk
Dvss
Dvdd
-002
Drxtx
Dclk
SYSclk
Dvss
Dvdd
Pin Type
Digital IO
Digital IO
Digital Output
Ground
Power
Description
Serial data input (transmit) or output (received)
Recovered clock output (data interface clock)
System clock output
Ground for the digital circuits
Vdd power for the digital circuits
-001 (control and status for the serial data interface)
-002 (decoupling capacitor pin for the internal regulator)
Bi-directional clock for the 2-wire serial interface
Bi-directional data for the 2-wire serial interface
Active low input interrupt that will immediately cause a Burst transmission
Output to the optional external loop filter
Input from the optional external loop filter
Ground for the local oscillator circuits
Negative side of the VCO tank
Positive side of the VCO tank
Vdd for the local oscillator circuits
Vdd power for the RF circuits
22
CoreReg
SSN
Digital
23
24
25
26
27
28
29
30
31
32
SCLK
SDATA
xBURST
LOOPout
LOOPin
LOvss
LOn
LOp
LOvdd
RFvdd
SCLK
SDATA
xBURST
LOOPout
LOOPin
LOvss
LOn
LOp
LOvdd
RFvdd
Digital
Digital
Digital Input
Analog
Analog
Ground
Analog
Analog
Power
Power
3.2.2. Block Diagram/Pin Definition
Figure 2: Block Diagram/Pin Definition *
* Not actual package markings. Please see marking format in 3.2.3.3.
13
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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