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參數(shù)資料
| 型號： | AMIS-53000-M |
| 英文描述： | Frequency Agile Transceiver |
| 中文描述： | 捷變頻收發(fā)器 |
| 文件頁數(shù)： | 85/99頁 |
| 文件大?。?/td> | 2638K |
| 代理商： | AMIS-53000-M |
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AMIS-53000
Frequency Agile Transceiver
Data Sheet
7.2.5. Use ID
Table 101: ID
Register
Number (HEX)
0X0C
0X0F
0X16
The chip ID is a 16 bit word which can be programmed in registers 3 and 4. In receive mode, when the use ID bit in general options A
is set, the AMIS-53000 will not begin exporting or buffering data until a valid ID matching the value stored in the chip address registers
is received. The ID is used in more advanced modes of operation for byte alignment. In addition to waking on its own unique ID, the
AMIS-53000 will also wake on a pre-defined global chip ID. The default value for the global ID is in the register table. This value can
be overwritten, but is not stored in EE so care must be taken when overwriting the value.
With the use ID bit enabled in transmit mode, the AMIS-53000 will transmit the chip ID prior to enabling the data interface. An
additional option bit in the TX config register allows selection of either the chip ID or global ID value for transmit.
In either transmit or receive, when the use ID bit is enabled without LOP enabled, the AMIS-53000 will not buffer data. Hence when
enabled stand alone, the data interface must be configured with the AMIS-53000 as the master.
Name
General Options A
TX Config
Burst Config
Bits
7
2
3
Function
Wake on ID in RX/send ID with TX
Select either the chip ID or global ID to be used in transmissions
Send ID with Burst packet
7.2.6. Length of Packet Enable
The length of packet enable (LOP) bit located in general options A, enables the AMIS-53000 to buffer packets. The use ID bit must be
used in conjunction with LOP to allow the receiver to byte align on incoming data.
In receive mode with the LOP enabled, the AMIS-53000 will interpret the first byte following either a valid chip ID, or global ID to be the
length of the incoming packet. This byte specifies the number of bytes following the LOP to be received (non-inclusive of the CRC if
enabled). When enabled, the AMIS-53000 will buffer the incoming packet into internal RAM. Following reception of the last byte of the
packet, an interrupt is issued on the interrupt pin, and depending on the configuration of the data interface, the packet will either be sent
out of the data interface by the AMIS-53000 as master, or wait for the external host/controller to stream the packet out as the master.
Having the LOP enabled in transmit mode allows for the use of the buffered TX packet option in transmit, or the AMIS-53000 can still
act as master and process the packet on the fly. With LOP enabled, and buffered TX disabled, the AMIS-53000 must be the master for
the data interface. In this mode, the preamble and chip ID (or global ID) will be sent before the data interface is activated. Once the
DSSN is pulled low by the AMIS-53000, the first byte received into the part is expected to be the LOP byte. Transmission continues
until the AMIS-53000 has determined that all bytes have been received, at which point the data interface is disabled, and the AMIS-
53000 will return to standby. When buffered TX is enabled, after the transmit instruction is given to the AMIS-53000, an interrupt from
the AMIS-53000 will be issued indicating the part is ready to load in the data packet. The actual loading of the data packet depends on
the data interface setup as to whether the AMIS-53000 is master or slave. The first byte is again expected to be the LOP byte. After
the complete packet is loaded into the radio, the RF will be enabled, the preamble and chip ID transmitted, followed by the packet.
After completion of the transmission, the AMIS-53000 will return to standby.
7.2.7. CRC Enable
The CRC enable located in general options A is the final tier of intelligence for the AMIS-53000 packet handling capability. In order for
the AMIS-53000 to do CRC checking, this option must be used in conjunction with both use ID and LOP enable. Operation of the
interface for both receive and transmit with the CRC enabled is no different from that explained under the LOP enabled section. With
the CRC enabled, the AMIS-53000 will append the calculated CRC in transmit as the last byte. In receive mode, interrupts to the
external controller will only be issued for packets passing the CRC.
85
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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