參數(shù)資料
型號(hào)： AMIS-53000-M
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁(yè)數(shù)： 46/99頁(yè)
文件大?。?/td> 2638K
代理商： AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
Setup registers descriptions:
Status
- Contains the results of calibrations, instructions and activity in the AMIS-53000.
Software State
- Shows the current mode of the AMIS-53000.
6.4.5.1.
Status/Flag1
The purpose of the Status1 register is to provide information back to the host on the status of the part. This register should be queried
at the completion of calibration sequences to ensure proper operation. The flags will be reset when the register is read.
CheckSum indicates whether an attempt to read or write the EE has failed due to an incorrect CheckSum.
Instruction enable indicates that the AMIS-53000 is ready to receive an instruction. This can be used to insure that the AMIS-53000
does not miss a command instruction due to the AMIS-53000 not being ready. Along with the busy flag, these status flags can police
the flow of commands to the AMIS-53000.
Table 29: Status/Flag1 - 0X01 [1]
Bit
Name
State
Comment
1
PLL out of lock on startup (RX, TX, Sniff, Burst)
7
PLL xLock
0
1
PLL calibration for transmit failed
6
TX PLL Cal
0
1
PLL calibration for receive failed
5
RX PLL Cal
0
1
10kHz RC oscillator calibration failed
4
RC Cal
0
1
Quick Start calibration failed
3
Quick Start Cal
0
1
EE CheckSum failed
2
CheckSum
0
1
The AMIS-53000 is in a state of operation that can accept instructions
1
Instruction Enable
0
1
ADC conversion complete
0
ADC Done
0
6.4.5.2.
Status/Flag2
The Status2 register provides information on the operating status of the part. The busy bit is asserted for any of the following reasons:
Calibration:
The busy bit will remain high for the duration of a calibration sequence. Status2 can be repeatedly polled during
a calibration sequence to determine when it’s complete.
Read/Write EE:
While the AMIS-53000 is reading from or writing to the EE, the busy bit will remain set.
Buffered RX:
When in receive mode, and a valid chip ID is found, the AMIS-53000 will begin processing of this packet.
During the time the packet is being processed, the busy bit will be set high.
Buffered TX:
After the command is given for transmit with the buffered packet option enabled, the busy bit will remain high
until the part has completed the actual transmission of the packet.
Housekeeping:
Busy is asserted during a housekeeping cycle.
Burst TX:
Busy is asserted during a Burst transmission.
46
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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