參數資料
型號: AMIS-53000-M
英文描述: Frequency Agile Transceiver
中文描述: 捷變頻收發(fā)器
文件頁數: 87/99頁
文件大?。?/td> 2638K
代理商: AMIS-53000-M
AMIS-53000
Frequency Agile Transceiver
Data Sheet
Figure 48: Data Interface Protocol (ID only)
7.2.9.2.
Use ID Enabled, No CRC, LOP Enabled
Table 105: Receive
Parameter
ID
LOP
No CRC
Table 106: Transmit
Parameter
Buffered
Transmit
Transmit
ID
Action
Data interface immediately ready after ID detected
Receiver loads rest of packet into buffer memory
After last data byte is received, radio returns to the previous state
An interrupt is issued to the external controller/microprocessor
Data is transferred out the port with the AMIS-53000 as master or the external controller as master
Error checking is not performed and CRC is not attached to packet
Action
If buffered transmit is selected, the AMIS-53000 will open the data interface and transfer all TX data
into memory with AMIS-53000 as master or external controller as master
Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transmits preamble (length of preamble as specified)
Transmits the SOF and the ID
Starts data interface and uses a synchronous clock to clock in the TX data (master only)
or clocks data out of memory (buffered TX)
After the packet is transmitted, the transmitter returns to standby state
87
AMI Semiconductor
– Aug. 05, Rev. 1.0
www.amis.com
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