
List of Tables
ix
21062E/0—June 1997
AMD K86 Family BIOS and Software Tools Developers Guide
Preliminary Information
List of Tables
Table 1.
Summary of AMD-K5 Processor CPU IDs and
BIOS Boot Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Summary of AMD-K6 MMX Enhanced Processor CPU IDs and
BIOS Boot Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . . . 9
SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SMM Revision Identifier Fields . . . . . . . . . . . . . . . . . . . . . . . . . 12
I/O Trap Dword Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Summary of Interrupts and Exceptions. . . . . . . . . . . . . . . . . . . 17
State of the AMD-K5 Processor After RESET. . . . . . . . . . . . . . 18
Segment Register Attribute Fields Initial Values . . . . . . . . . . 20
Hardware Configuration Register (HWCR) Fields. . . . . . . . . . 23
BIST Error Bit Definition in EAX Register . . . . . . . . . . . . . . . . 25
Array IDs in Array Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Branch-Trace Message Special Bus Cycle Fields . . . . . . . . . . . 39
AMD-K5 Processor Device Identification Register . . . . . . . . . 45
Public TAP Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Control Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Boundary Scan Register Bit Definitions . . . . . . . . . . . . . . . . . . 49
Control Register 4 (CR4) Fields . . . . . . . . . . . . . . . . . . . . . . . . . 59
Page-Directory Entry (PDE) Fields . . . . . . . . . . . . . . . . . . . . . . 64
Page-Table Entry (PTE) Fields. . . . . . . . . . . . . . . . . . . . . . . . . . 66
Virtual-Interrupt Additions to EFLAGS Register . . . . . . . . . . 71
Instructions that Modify the IF or VIF Flags—Real Mode . . . 71
Instructions that Modify the IF or VIF Flags—Protected
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Instructions that Modify the IF or VIF Flags—Virtual-8086
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Instructions that Modify the IF or VIF Flags—Virtual-8086
Mode Interrupt Extensions (VME). . . . . . . . . . . . . . . . . . . . . . . 74
Instructions that Modify the IF or VIF Flags—Protected
Mode Virtual Interrupt Extensions (PVI) . . . . . . . . . . . . . . . . . 75
Interrupt Behavior and Interrupt-Table Access . . . . . . . . . . . . 78
Machine-Check Type Register (MCTR) Fields . . . . . . . . . . . . . 81
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . . 97
AMD-K6 Processor State-Save Map . . . . . . . . . . . . . . . . . . . . . . 98
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
AMD-K6 Processor I/O Trap Dword Configuration. . . . . . . . . 101
State of the AMD-K6 Processor After RESET. . . . . . . . . . . . . 102
Data Returned by the CPUID Instruction . . . . . . . . . . . . . . . . 105
Boundary Scan Register Bit Definitions . . . . . . . . . . . . . . . . . 109
AMD-K6 Processor Device Identification Register . . . . . . . . 110
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.