
AMD-K5 Processor
39
21062E/0—June 1997
AMD K86 Family BIOS and Software Tools Developers Guide
Preliminary Information
Debug Compatibility
with the Pentium
Processor
The differences in debug functions between the AMD-K5
processor and Pentium are described in Appendix A of the
AMD-K5 Processor Technical Reference Manual,
order# 18524.
Branch Tracing
Branch tracing is enabled by writing bits 3–1 with 001b and
setting bit 5 to 1 (disabling branch prediction) in the Hardware
Configuration Register (HWCR), as described on page 22.
When thus enabled, the processor drives two branch-trace
message special bus cycles immediately after each taken
branch instruction is executed. Both special bus cycles have a
BE7–BE0 encoding of DFh (1101_1111b). The first special bus
cycle identifies the branch source, the second identifies the
branch target. The contents of the address and data bus during
these special bus cycles are shown in Table 14.
The branch-trace message special bus cycles are different for
the AMD-K5 processor and Pentium, although their BE7–BE0
encodings are the same.
Table 14. Branch-Trace Message Special Bus Cycle Fields
Signals
A31
First Special Bus Cycle
0 = First special bus cycle (source)
Second Special Bus Cycle
1 = Second special bus cycle (target)
Operating Mode of Target:
11 = Virtual-8086 Mode
10 = Protected Mode
01 = Not valid
00 = Real Mode
Default Operand Size of Target Segment:
1 = 32-bit
0 = 16-bit
0
A30–A29
Not valid
A28
Not valid
A27–A20
A19–A4
A3
D31–D0
0
Code Segment (CS) selector of Branch Source Code Segment (CS) Selector of Branch Target
0
EIP of Branch Source
0
EIP of Branch Target