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參數(shù)資料
| 型號： | AMDK86 |
| 英文描述： | AMD K86 - AMD K86 Family BIOS and Software Tools Developers Guide |
| 中文描述： | AMD的K86 - AMD的K86系列BIOS和軟件工具開發(fā)人員指南 |
| 文件頁數(shù)： | 52/144頁 |
| 文件大?。?/td> | 2179K |
| 代理商： | AMDK86 |
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AMD-K5 Processor
AMD K86 Family BIOS and Software Tools Developers Guide
21062E/0—June 1997
Preliminary Information
Functional-Redundancy Checking
When FRCMC is asserted at RESET, the processor enters
Functional-Redundancy Checking mode as the checker and
reports checking errors on the IERR output. If FRCMC is
negated at RESET, the processor operates normally, although
it also behaves as the master in a functional-redundancy
checking arrangement with a checker.
In the Functional-Redundancy Checking mode, two processors
have their signals tied together. One processor (the master)
operates normally. The other processor (the checker) has its
output and bidirectional signals (except for TDO and IERR)
floated to detect the state of the master’s signals. The master
controls instruction fetching and the checker mimics its
behavior by sampling the fetched instructions as they appear
on the bus. Both processors execute the instructions in lock
step. The checker compares the state of the master’s output and
bidirectional signals with the state that the checker itself
would have driven for the same instruction stream.
Errors detected by the checker are reported on the IERR
output of the checker. If a mismatch occurs on such a
comparison, the checker asserts IERR for one clock, two clocks
after the detection of the error. Both the master and the
checker continue running the checking program after an error
occurs. No action other than the assertion of IERR is taken by
the processor. On the AMD-K5 processor, the IERR output is
reserved solely for functional-redundancy checking. No other
errors are reported on that output.
Functional-redundancy checking is typically implemented on
single-processor, fault-monitoring systems (which have two
processors). The master processor runs the operational
programs and the checker processor is dedicated entirely to
constant checking. In this arrangement, the accurate operation
test consists solely of reporting one or more errors. The
particular error type or the instruction causing an error is not
reported. The arrangement works because the processor is
entirely deterministic. Speculative prefetching, speculative
execution, and cache replacement all occur in identical ways
and at identical times on both processors if their signals are
tied together so that they run the same program.
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