參數(shù)資料
型號(hào): AMDK86
英文描述: AMD K86 - AMD K86 Family BIOS and Software Tools Developers Guide
中文描述: AMD的K86 - AMD的K86系列BIOS和軟件工具開發(fā)人員指南
文件頁數(shù): 19/144頁
文件大?。?/td> 2179K
代理商: AMDK86
AMD-K5 Processor
7
21062E/0—June 1997
AMD K86 Family BIOS and Software Tools Developers Guide
Preliminary Information
AMD-K5 Processor System Management Mode (SMM)
System Management Mode (SMM) is an alternate operating
mode entered by way of a system management interrupt (SMI)
and handled by an interrupt service routine. SMM is designed
for system control activities such as power management. These
activities appear transparent to conventional operating
systems like DOS and Windows. SMM is primarily targeted for
use by the Basic Input Output System (BIOS) and specialized
low-level device drivers. The code and data for SMM are stored
in the SMM memory area, which is isolated from main memory.
The processor enters SMM by the system logic’s assertion of the
SMI# interrupt and the processor’s acknowledgment by the
assertion of SMIACT#. At this point the processor saves its
state into the SMM memory state-save area and jumps to the
SMM service routine. The processor returns from SMM when it
executes the RSM (resume) instruction from within the SMM
service routine. Subsequently, the processor restores its state
from the SMM save area, de-asserts SMIACT#, and resumes
execution with the instruction following the point where it
entered SMM.
The following sections summarize the SMM state-save area,
entry into and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
Operating Mode and Default Register Values
The software environment within SMM has the following
characteristics:
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Addressing and operation in Real mode
4-Gbyte segment limits
Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
Control transfers that do not override the default operand
size truncate the EIP to 16 bits
Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in Real mode
segment-base addressing
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