
38
AMD-K5 Processor
AMD K86 Family BIOS and Software Tools Developers Guide
21062E/0—June 1997
Preliminary Information
Debug Registers
The processor implements the standard debug functions and
registers—DR7–DR6 and DR3–DR0 (often called DR7–DR0)—
available on the 486 processor, plus an I/O breakpoint
extension.
Standard Debug
Functions
The debug functions make the processor’s state visible to
debug software through four debug registers (DR3–DR0) that
are accessed by MOV instructions. Accesses to memory
addresses can be set as breakpoints in the instruction flow by
invoking one of two debug exceptions (interrupt vectors 1 or 3)
during instruction or data accesses to the addresses. The debug
functions eliminate the need to embed breakpoints in code and
allow debugging of ROM as well as RAM.
For details on the standard 486 debug functions and registers,
see the AMD documentation on the Am486
processor or other
commercial x86 literature.
I/O Breakpoint
Extension
The processor supports an I/O breakpoint extension for
breakpoints on I/O reads and writes. This function is enabled by
setting bit 3 of CR4, as described in “Control Register 4 (CR4)
Extensions” on page 58. When enabled, the I/O breakpoint
function is invoked by the following:
I
Entering the I/O port number as a breakpoint address
(zero-extended to 32 bits) in one of the breakpoint registers,
DR3–DR0
Entering the bit pattern, 10b, in the corresponding 2-bit
read-write (R/W) field in DR7
I
All data breakpoints on the AMD-K5 processor are precise,
including those encountered in repeated string operations. The
trap is taken after completing the iteration on which the
breakpoint match occurs.
Enabled breakpoints slow the processor somewhat. When a
data breakpoint is enabled, the processor disables its dual-issue
load/store operations and performs only single-issue load/store
operations. When an instruction breakpoint is enabled,
instruction issue is completely serialized.