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參數(shù)資料
| 型號： | AMDK86 |
| 英文描述： | AMD K86 - AMD K86 Family BIOS and Software Tools Developers Guide |
| 中文描述： | AMD的K86 - AMD的K86系列BIOS和軟件工具開發(fā)人員指南 |
| 文件頁數(shù)： | 60/144頁 |
| 文件大?。?/td> | 2179K |
| 代理商： | AMDK86 |
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48
AMD-K5 Processor
AMD K86 Family BIOS and Software Tools Developers Guide
21062E/0—June 1997
Preliminary Information
RUNBIST.
This version of BIST is similar to the normal BIST
mode, except RUNBIST is started by shifting in a TAP
instruction. This instruction should behave according to the
rules of the IEEE 1149.1 definition of RUNBIST.
When the RUNBIST instruction is updated into the instruction
register, a signal from the TAP_RTL block called JTGBIST is
asserted High. This signal goes to the PAD_TOP and
TESTCTRL blocks. In PAD_TOP, this signal goes to the
BRNBIST block and causes both INIT_SAMP and RUNBIST to
be asserted. To the rest of the processor, it looks like a normal
BIST operation is taking place. The JTGBIST signal also goes to
the TESTCTRL block so the BIST controller knows the BIST
operation was initiated from the TAP controller. This operation
is necessary because the BIST results do not get transferred to
the EAX register in this mode of operation. The JTAG_BIST
block also asserts the RESET_TAP pin to the CLOCKS block for
15 system clock cycles in order to fake an external reset.
The pattern that is shifted into the boundary scan ring prior to
the selection of the RUNBIST instruction is driven at output
and bidirectional cells during the duration of the instruction.
The results of the execution of RUNBIST are saved in the BIST
results register, which is 9 bits long and looks like the least
significant 9 bits in the EAX register. This register is selected
for shifting between TDI and TDO and can be shifted out after
the completion of BIST. Bit 0 (ICACHE data status) is shifted
out first. The BIST results should be independent of signals
received at non-clock input pins (except for RESET).
BYPASS.
The execution of the BYPASS instruction connects the
bypass register between TDI and TDO, bypassing the test logic.
Because of the pull-up resistor on the TDI input, the bypass
register is selected if there is an open circuit in the board-level
test data path following an instruction scan cycle. Any unused
instruction bit patterns cause the bypass register to be selected
for shifting between TDI and TDO.
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