
AMD-K5 Processor
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21062E/0—June 1997
AMD K86 Family BIOS and Software Tools Developers Guide
Preliminary Information
the timing signal for data transfer and system architecture
operation.
The dedicated TCK input enables the serial test data path
between components to be used independently of
component-specific system clocks. TCK also ensures that test
data can be moved to or from a chip without changing the state
of the on-chip system logic.
The TCK signal is driven by an independent 50% duty cycle
clock (generated by the Automatic Test Equipment). If the TCK
must be stopped (for example, if the ATE must retrieve data
from external memory and is unable to keep the clock running),
it can be stopped at 0 or 1 indefinitely, without causing any
change to the test logic state.
To ensure race-free operation, changes on the TAP’s TMS input
are clocked into the test logic. Changes on the TAP’s TDI input
are clocked into the selected register (Instruction or Test Data
Register) on the rising edge of TCK. The contents of the
selected register are shifted out onto the TAP output (TDO) on
the falling edge of TCK.
Registers
Boundary scan architectural elements include an Instruction
Register (IR) and a group of Test Data Registers (TDRs). These
registers have separate shift-register-based serial access paths
connected in parallel between the TDI and TDO pins.
The TDRs are internal registers used by the Boundary Scan
Architecture to process the test data. Each Test Data Register
is addressed by an instruction scanned into the Instruction
Register. The AMD-K5 processor includes the following TDRs:
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Bypass Register (BR). See “Bypass Register” on page 45.
Boundary Scan Register (BSR). See “Boundary Scan
Register” on page 44.
Device Identification Register (DIR). See “Device
Identification Register” on page 45.
Built-In Self-Test Result Register (BISTRR). See
“RUNBIST” on page 48.
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