
AMD-K5 Processor
65
21062E/0—June 1997
AMD K86 Family BIOS and Software Tools Developers Guide
Preliminary Information
Global Pages
The AMD-K5 processor supports global paging only on Models
1, 2, and 3, with a Stepping of 4 or greater.
The processor’s performance can sometimes be improved by
making some pages
global
to all tasks and procedures. This can
be done for both 4-Kbyte pages and 4-Mbyte pages.
The processor invalidates (flushes) both the 4-Kbyte TLB and
the 4-Mbyte TLB whenever CR3 is loaded with the base address
of the new task’s page directory. The processor loads CR3
automatically during task switches, and the operating system
can load CR3 at any other time. Unnecessary invalidation of
certain TLB entries can be avoided by specifying those entries
as
global
(a global TLB entry references a
global page)
. This
improves performance after TLB flushes. Global entries remain
in the TLB and need not be reloaded. For example, entries may
reference operating system code and data pages that are
always required. The processor operates faster if these entries
are retained across task switches and procedure calls.
To specify individual pages as
global:
1. Set the Global Page Extension (GPE) bit in CR4.
2. (Optional) Set the Page Size Extension (PSE) bit in CR4.
3. Set the relevant Global (G) bit for that page:
For 4-Kbyte pages
—Set the G bit in both the page-directory
entry (shown in Figure 16 and Table 20) and the page-table
entry (shown in Figure 17 and Table 21).
For 4-Mbyte pages
—(Optional) After the PSE bit in CR4 is
set, set the G bit in the page-directory entry (shown in
Figure 16 and Table 20).
4. Load CR3 with the base address of the page directory.
The INVLPG instruction clears both the V and G bits for the
referenced entry. To invalidate all entries in both TLBs,
including global-page entries:
1. Clear the Global Page Extension (GPE) bit in CR4.
2. Load CR3 with the base address of another (or same) page
directory.