參數(shù)資料
型號(hào): AMDK86
英文描述: AMD K86 - AMD K86 Family BIOS and Software Tools Developers Guide
中文描述: AMD的K86 - AMD的K86系列BIOS和軟件工具開發(fā)人員指南
文件頁數(shù): 40/144頁
文件大?。?/td> 2179K
代理商: AMDK86
28
AMD-K5 Processor
AMD K86 Family BIOS and Software Tools Developers Guide
21062E/0—June 1997
Preliminary Information
Array Access Register
(AAR)
The 64-bit Array Access Register (AAR) is a MSR that contains
a 32-bit
array pointer
that identifies the array location to be
tested and 32 bits of
array test data
to be read or written. The
WRMSR and RDMSR instructions access the AAR when the
ECX register contains the value 82h, as described on page 90.
Figure 3 shows the format of the AAR.
Figure 3. Array Access Register (AAR)
To read or write an array location, perform the following steps:
1.
ECX
—Enter 82h into ECX to access the 64-bit AAR.
2.
EDX
—Enter a 32-bit
array pointer
into EDX, as shown in
Figures 4 through 12 (top).
3.
EAX
—Read or write 32 bits of
array test data
to or from
EAX, as shown in Figures 4 through 12 (bottom).
Array Pointer
The array pointers entered in EDX (Figures 4 through 12, top)
specify particular array locations. For example, in the data- and
instruction-cache arrays, the way (or column) and set (or index)
in the array pointer specify a cache line in the 4-way,
set-associative array. The array pointers for data-cache data
and instruction-cache instructions also specify a dword location
within that cache line. In the data cache, this dword is 32 bits of
data; in the instruction cache, this dword is two instruction
bytes plus their associated pre-decode bits. For the 4-Kbyte
TLB, the way and set specify one of the 128 TLB entries. In
4-Mbyte TLB, one of only four entries is specified.
Bits 7–0 of every array pointer encode the
array ID
, which
identifies the array to be accessed, as shown in Table 13. To
simplify multiple accesses to an array, the contents of EDX are
MSR
82h
0
31
0
31
Array Pointer
(Contents of EDX)
Array Data
(Contents of EAX)
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