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| 型號(hào)： | AMDK86 |
| 英文描述： | AMD K86 - AMD K86 Family BIOS and Software Tools Developers Guide |
| 中文描述： | AMD的K86 - AMD的K86系列BIOS和軟件工具開(kāi)發(fā)人員指南 |
| 文件頁(yè)數(shù)： | 29/144頁(yè) |
| 文件大?。?/td> | 2179K |
| 代理商： | AMDK86 |
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AMD-K5 Processor
17
21062E/0—June 1997
AMD K86 Family BIOS and Software Tools Developers Guide
Preliminary Information
Table 8.
Summary of Interrupts and Exceptions
Priority
Description
INTn instruc-
tions and all
other software
exceptions
BUSCHK#
R/S#
Type
Sampling
5
Vector
1
Acknowledgment
Point of Interruptibility
6
1
exceptions
internal
0–255
none
Entry to service routine
2
3
interrupt
interrupt
level-sensitive
level-sensitive
18
2
none
none
PRDY
Entry to service routine
2
Negation of PRDY
4
FLUSH#
interrupt
edge-triggered
4
none
FLUSH#-Acknowl-
edge special
bus cycle
BRDY# of FLUSH#
Acknowledge bus cycle
5
SMI#
interrupt
edge-triggered
4
SMM
3
SMIACT#
Entry to SMM service
routine
7
Completion of
initialization
NMI interrupts: IRET from
service routine. All others:
Entry to service routine.
6
INIT
interrupt
edge-triggered
4
BIOS
none
7
NMI
interrupt
edge-triggered
4
2
none
8
INTR
interrupt
level-sensitive
0–255
Interrupt acknowl-
edge special
bus cycle
Stop-Grant
special bus cycle
Entry to service routine
9
STPCLK#
interrupt
level-sensitive
none
Negation of STPCLK#
Notes:
1. For interrupts with vectors, the processor saves its state prior to accessing the service routine and changing the program flow.
Interrupts without vectors do not change program flow; instead, they simply pause program flow for the duration of the interrupt
function and return to where they left off.
2. If the Machine Check Enable (MCE) bit in CR4 is set to 1.
3. The entry point for the SMI interrupt handler is at offset 8000h from the SMM Base Address.
4. Only the edge-triggered interrupts are latched when asserted. All interrupts are recognized at the next instruction retirement
boundary.
5. If a bus cycle is in progress, EWBE must be asserted before the interrupt is recognized.
6. For external interrupts (most exceptions, by contrast, are recognized when they occur). External interrupts are recognized at
instruction boundaries. When MOV or POP instructions load SS, interruptibility is delayed until after the next instruction, thus
allowing both SS and the corresponding SP to load.
7. After assertion of SMI, subsequent assertions of SMI are masked to prevent recursive entry into SMM. However, other exceptions
or interrupts (except INIT and NMI) are taken in the SMM service routine.
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