
List of Figures
xiii
22548B/0
—
August 1999
AMD-756
Peripheral Bus Controller Data Sheet
Preliminary Information
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
AMD-750
Chipset System Block Diagram . . . . . . . . . . . . . . . 2
AMD-756
Peripheral Bus Controller Block Diagram . . . . . . 8
AMD-756
Peripheral Bus Controller Signal Groups. . . . . . 14
I/O Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
I/O Cycle 16-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . . . . . 66
Non-Posted PCI-to-ISA Access . . . . . . . . . . . . . . . . . . . . . . . . . 67
Posted PCI-to-Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ISA Bus Memory Access Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 69
ISA Bus Memory Cycle: 16-Bit to 8-Bit Conversion . . . . . . . . 70
Memory Cycle 32-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . 71
Memory Cycle 32-Bit to 16-Bit Conversion . . . . . . . . . . . . . . . 72
ROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ROM Cycle 32-Bit to 8-Bit Conversion . . . . . . . . . . . . . . . . . . 74
Configuration Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Configuration Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Subtractive Decode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DMA Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ISA Bus Master Arbitration Timing . . . . . . . . . . . . . . . . . . . . 81
ISA Bus Master-to-PCI Memory (Memory Read) . . . . . . . . . .82
ISA Bus Master-to-PCI Memory (Memory Write). . . . . . . . . .82
Normal Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .90
Type F DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DMA Ready Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
IDE Controller Connections. . . . . . . . . . . . . . . . . . . . . . . . . . 106
Power Management and General Purpose I/O . . . . . . . . . . . 111
Basic Power Management Block Diagram . . . . . . . . . . . . . .112
SCI/SMI Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Power State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Mechanical Off to Full On . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Soft Off to Full On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
General-Purpose I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
FPIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144