- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C971 (Advanced Micro Devices, Inc.) PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus PDF資料下載
參數(shù)資料
| 型號： | AM79C971 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線 |
| 文件頁數(shù)： | 78/265頁 |
| 文件大?。?/td> | 3190K |
| 代理商： | AM79C971 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當(dāng)前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁
78
Am79C971
The MII Management Interface has a built-in detection
system to allow the Am79C971 controller to determine
if an external PHY is attached. The MDIO I/O pin has a
resistor network between the Am79C971 controller and
the external PHY that will assert a static 1 when
connected. If there is no external PHY connected, the
resistor network will drive a static zero. This information
is signaled by the interrupt MPDTINT (CSR7, MIIPDTI,
bit 1), and the status is provided by reading the Media
Independent Interface PHY Detected (MIIPD) (BCR32,
bit 14). This resistor network is only required on an
exposed MII connector.
MII Management Frames
MII management frames are automatically generated
by the Am79C971 controller and conform to the MII
clause in the IEEE 802.3u standard.
The start of the frame is a preamble of 32 ones and
guarantees that all of the external PHYs are synchro-
nized on the same interface. (See Figure 39.) Loss of
synchronization is possible due to the
hot-plugging
ca-
pability of the exposed MII.
The IEEE 802.3 specification allows you to drop the
preamble, if after reading the MII Status Register from
the external PHY you can determine that the external
PHY will support Preamble Suppression (BCR34, bit
6). After having a valid MII Status Register read, the
Am79C971 controller will then drop the creation of the
preamble stream until a reset occurs, receives a read
error, or the external PHY is disconnected.
Figure 39.
Frame Format at the MII Interface Connection
This is followed by a start field (ST) and an operation
field (OP). The operation field (OP) indicates whether
the Am79C971 controller is initiating a read or write op-
eration. This is followed by the external PHY address
(PHYAD) and the register address (REGAD) pro-
grammed in BCR33. The internal PHYAD is at location
1Fh and the internal register address space REGAD is
00h - 08h. The external PHY may have a larger ad-
dress space starting at 10h - 1Fh. This is the address
range set aside by the IEEE as vendor usable address
space and will vary from vendor to vendor. This field is
followed by a bus turnaround field. During a read oper-
ation, the bus turnaround field is used to determine if
the external PHY is responding correctly to the read re-
quest or not. The Am79C971 controller will tri-state the
MDIO for both MDC cycles. During the second cycle, if
the external PHY is synchronized to the Am79C971
controller, the external PHY will drive a 0. If the external
PHY does not drive a 0, the Am79C971 controller will
signal a MREINT (CSR7, bit 9) interrupt, if MREINTE
(CSR7, bit 8) is set to a 1, indicating the Am79C971
controller had an MII management frame read error
and that the data in BCR34 is not valid. The data field
to/from the internal or external PHY is read or written
into the BCR34 register. The last field is an IDLE field
that is necessary to give ample time for drivers to turn
off before the next access. The Am79C971 controller
will drive the MDC to 0 and tri-state the MDIO anytime
the MII Management Port is not active.
To help to speed up the reading and writing of the MII
management frames to the external PHY, the MDC can
be sped up to 10 MHz by setting the FMDC bits in
BCR32. The IEEE 802.3 specification requires use of
the 2.5-MHz clock rate, but 5 MHz and 10 MHz are
available for the user. The intended applications are
that the 10-MHz clock rate can be used for a single ex-
ternal PHY on an adapter card or motherboard. The 5-
MHz clock rate can be used for an exposed MII with
one external PHY attached. The 2.5-MHz clock rate is
intended to be used when multiple external PHYs are
connected to the MII Management Port or if compli-
ance to the IEEE 802.3u standard is required.
Auto-Poll External PHY Status Polling
As defined in the IEEE 802.3 standard, the external
PHY attached to the Am79C971 controller
’
s MII has no
way of communicating important timely status informa-
tion back to Am79C971 controller. The Am79C971
controller has no way of knowing that an external PHY
has undergone a change in status without polling the
MII status register. To prevent problems from occurring
with inadequate host or software polling, the
Am79C971 controller will Auto-Poll when APEP
(BCR32, bit 11) is set to 1 to insure that the most cur-
rent information is available. See
Appendix E, Auto Ne-
Preamble
1111....1111
OP
10 Rd
01 Wr
PHY
Address
Register
Address
TA
Z0 Rd
10 Wr
Data
Idle
Z
2
Bits
5
Bits
5
Bits
2
Bits
32
Bits
miiframe
ST
01
2
Bits
16
Bits
1
Bit
20550D-42
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972 | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C971AKC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C971AVC | 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays |
| AM79C971AVC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AVC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。