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參數(shù)資料
| 型號： | AM79C971 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線 |
| 文件頁數(shù)： | 68/265頁 |
| 文件大小： | 3190K |
| 代理商： | AM79C971 |
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68
Am79C971
Since any valid Ethernet Type field value will always be
greater than a normal IEEE 802.3 Length field (
≥
46),
the Am79C971 controller will not attempt to strip valid
Ethernet frames.
Note that for some network protocols,
the value passed in the Ethernet Type and/or IEEE
802.3 Length field is not compliant with either standard
and may cause problems if pad stripping is enabled
.
Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the Am79C971 controller.
Note that if the Automatic Pad Stripping feature is en-
abled, the FCS for padded frames will be verified
against the value computed for the incoming bit stream
including pad characters, but the FCS value for a pad-
ded frame will not be passed to the host. If an FCS
error is detected in any frame, the error will be reported
in the CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories, i.e., those conditions which are the
result of normal network operation, and those which
occur due to abnormal network and/or host related
events.
Normal events which may occur and which are handled
autonomously by the Am79C971 controller are basi-
cally collisions within the slot time and automatic runt
packet rejection. The Am79C971 controller will ensure
that collisions that occur within 512 bit times from the
start of reception (excluding preamble) will be automat-
ically deleted from the receive FIFO with no host inter-
vention. The receive FIFO will delete any frame that is
composed of fewer than 64 bytes provided that the
Runt Packet Accept (RPA bit in CSR124) feature has
not been enabled and the network interface is operat-
ing in half-duplex mode. This criterion will be met re-
gardless of whether the receive frame was the first (or
only) frame in the FIFO or if the receive frame was
queued behind a previously received message.
Abnormal network conditions include:
I
FCS errors
I
Late collision
Host related receive exception conditions include
MISS, BUFF, and OFLO. These are described in the
section,
Buffer Management Unit
.
Loopback Operation
Loopback is a mode of operation intended for system
diagnostics. In this mode, the transmitter and receiver
are both operating at the same time so that the control-
ler receives its own transmissions. The controller pro-
vides two basic types of loopback. In internal loopback
mode, the transmitted data is looped back to the re-
ceiver inside the controller without actually transmitting
any data to the external network. The receiver will
move the received data to the next receive buffer,
where it can be examined by software. Alternatively, in
external loopback mode, data can be transmitted to
and received from the external network.
Loopback operation is enabled by setting LOOP
(CSR15, bit 2) to 1. The mode of loopback operation is
dependent on the active network port and on the set-
tings of the control bits INTL (CSR15, bit 6), MENDECL
(CSR15, bit 10), and TMAULOOP (BCR2, bit 14). The
setting of the full-duplex control bits in BCR9 has no ef-
fect on the loopback operation.
GPSI Loopback Modes
When GPSI is the active network port, there are only
two modes of loopback operation: internal and external
loopback. The settings of MENDECL and TMAULOOP
have no effect for this port.
When INTL is set to 1, internal loopback is selected.
Data coming out of the transmit FIFO is fed directly to
the receive FIFO. All GPSI outputs are inactive; inputs
are ignored.
External loopback operation is selected by setting INTL
to 0. Data is transmitted to the network and is expected
to be looped back to the GPSI receive pins outside the
chip. Collision detection is active in this mode.
AUI Loopback Modes
When AUI is the active network port, there are three
modes of loopback operation: internal with and without
MENDEC and external loopback. The setting of TMAU-
LOOP has no effect for this port.
When INTL and MENDECL are set to 1, internal loop-
back without MENDEC is selected. Data coming out of
the transmit FIFO is fed directly to the receive FIFO.
The AUI transmitter is disabled and signals on the re-
ceive and collision inputs are ignored.
When INTL is set to 1 and MENDECL is cleared to 0,
internal loopback including the MENDEC is selected.
Data is routed from the transmit FIFO through the
MENDEC back to the receive FIFO. No data is trans-
mitted to the network. All signals on the receive and
collision inputs are ignored.
External loopback operation is selected by setting INTL
to 0. The programming of MENDECL has no effect in
this mode. The AUI transmitter is enabled and data is
transmitted to the network. The Am79C971 controller
expects data to be looped back to the receive inputs
outside the chip. Collision detection is active in this
mode.
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| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C971AKC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C971AVC | 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays |
| AM79C971AVC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AVC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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