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70
Am79C971
Manchester Encoder/Decoder
The integrated Manchester Encoder/Decoder (MEN-
DEC) provides the PLS (Physical Layer Signaling)
functions required for a fully compliant ISO 8802-3
(IEEE/ANSI 802.3) station. The MENDEC provides the
encoding function for data to be transmitted on the net-
work using the high accuracy on-board oscillator,
driven by either the crystal oscillator or an external
CMOS-level compatible clock. The MENDEC also pro-
vides the decoding function from data received from
the network. The MENDEC contains a Power On Reset
(POR) circuit, which ensures that all analog portions of
the Am79C971 controller are forced into their correct
state during power up, and prevents erroneous data
transmission and/or reception during this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the follow-
ing crystal specification (Table 7) may be used to en-
sure less than
±
0.5 ns jitter at DO
±
.
Note:
*
Requires trimming specification; not trim is 50 PPM total.
External Clock Drive Characteristics
When driving the oscillator from a CMOS-level external
clock source, XTAL2 must be left floating (uncon-
nected). An external clock having the following charac-
teristics must be used to ensure less than
±
0.5 ns jitter
at DO
±
. See Table 8.
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO
±
) are de-
signed to operate into terminated transmission lines.
When operating into a 78-
terminated transmission
line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet, and IEEE-
802.3.
Transmitter Timing and Operation
A 20-MHz fundamental mode crystal oscillator pro-
vides the basic timing reference for the MENDEC por-
tion of the Am79C971 controller. The crystal frequency
is divided by two to create the internal transmit clock
reference. Both the 10-MHz and 20-MHz clocks are fed
into the Manchester Encoder. The internal transmit
clock is used by the MENDEC to synchronize the Inter-
nal Transmit Data (ITXDAT) and Internal Transmit En-
able (ITXEN) from the controller. The internal transmit
clock is also used as a stable bit rate clock by the re-
ceive section of the MENDEC and controller.
The oscillator requires an external 0.01% timing refer-
ence. If an external crystal is used, the accuracy re-
quirements are tighter because allowance for the on-
board parasitics must be made to deliver a final accu-
racy of 0.01%.
Transmission is enabled by the controller. As long as
the ITXEN request remains active, the serial output of
the controller will be Manchester encoded and appear
at DO
±
. When the internal request is dropped by the
controller, the differential transmit outputs go to one of
two idle states, dependent on TSEL in the Mode Reg-
ister (CSR15, bit 9).
Table 9.
TSEL Effect
Table 7.
Crystal Characteristics
Parameter
1. Parallel Resonant
Frequency
2. Resonant
Frequency Error
3. Change in
Resonant Frequency
With Respect To
Temperature
(0 - 70 C)
*
4. Crystal Load
Capacitance
5. Motional Crystal
Capacitance (C1)
6. Internal Equivalent
Series Resistance
7. Shunt
Capacitance
Min
Nom
Max
Units
20
MHz
-50
+50
PPM
-40
+40
PPM
20
50
pF
0.022
pF
35
ohm
7
pF
Table 8.
External Clock Source Characteristics
Clock Frequency:
20 MHz
±
0.01%
<= 6 ns from 0.5 V to VDD
-0.5 V
Rise/Fall Time (tR/tF):
XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
XTAL1 Falling Edge to
Falling Edge Jitter:
20 ns min.
<
±
0.2 ns at 2.5 V input
(VDD/2)
TSEL LOW:
The idle state of DO
±
yields 0 differential
to operate transformer-coupled loads.
In this idle state, DO+ is positive with
respect to DO- (logical HIGH).
TSEL HIGH: