參數(shù)資料
型號(hào)： AM79C971
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述： PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線
文件頁(yè)數(shù)： 130/265頁(yè)
文件大小： 3190K
代理商： AM79C971
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130
Am79C971
15-0
PADR[15:0] Physical
Address
Register,
PADR[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR13: Physical Address Register 1
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[31:16] Physical
Address
Register,
PADR[31:16]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR14: Physical Address Register 2
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
PADR[47:32] Physical
Address
Register,
PADR[47:32]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
CSR15: Mode
This register
’
s fields are loaded during the Am79C971
controller initialization routine with the corresponding
Initialization Block values, or when a direct register
write has been performed on this register.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
PROM
Promiscuous
PROM = 1, all incoming receive
frames are accepted.
Mode.
When
Read/Write accessible only when
either the STOP or the SPND bit
is set.
14
DRCVBC
Disable
When
Am79C971 controller from re-
ceiving broadcast messages.
Used for protocols that do not
support broadcast addressing,
except as a function of multicast.
DRCVBC is cleared by activation
of
H_RESET
(broadcast messages will be re-
ceived) and is unaffected by
STOP.
Receive
set,
Broadcast.
disables
the
or
S_RESET
Read/Write accessible only when
either the STOP or the SPND bit
is set.
13
DRCVPA
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the Am79C971 controller
will be disabled. Frames ad-
dressed to the nodes individual
physical address will not be rec-
ognized.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
12
DLNKTST
Disable
DLNKTST = 1, monitoring of Link
Pulses
is
disabled.
DLNKTST = 0, monitoring of Link
Pulses is enabled. This bit only
has meaning when the 10BASE-
T network interface is selected.
Link
Status.
When
When
Read/Write accessible only when
either the STOP or the SPND bit
is set.
11
DAPC
Disable Automatic Polarity Cor-
rection. When DAPC = 1, the
相關(guān)PDF資料
PDF描述
AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
AM79C972BKCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
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參數(shù)描述
AM79C971AKC 制造商:Advanced Micro Devices 功能描述:
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AM79C971AVC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C971AWW WAF 制造商:Advanced Micro Devices 功能描述:
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