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參數(shù)資料
| 型號(hào)： | AM79C971 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線 |
| 文件頁(yè)數(shù)： | 72/265頁(yè) |
| 文件大小： | 3190K |
| 代理商： | AM79C971 |
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72
Am79C971
The time delay from the last rising edge of the message
to IRXEN deassert allows the last bit to be strobed by
IRXCLK and transferred to the controller section, but
prevents any extra bit(s) at the end of message.
Data Decoding
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI
±
inputs. Input
error is less than
±
35 mV to minimize sensitivity to input
rise and fall time. IRXCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following IRXCLK. The data receiver also gener-
ates the signal used for phase detector comparison to
the internal MENDEC VCO.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with
the values 1010b. The clock is phase-locked to the neg-
ative transition at the bit cell center of the second zero
in the pattern.
Since data is strobed at 1/4 bit time, Manchester tran-
sitions which shift from their nominal placement
through 1/4 bit time will result in improperly decoded
data. With this as the criterion for an error, a definition
of Jitter Handling is:
The peak deviation approaching or crossing 1/4 bit
cell position from nominal input transition, for which
the MENDEC section will properly decode data.
Attachment Unit Interface
The Attachment Unit Interface (AUI) is the PLS (Physi-
cal Layer Signaling) to PMA (Physical Medium Attach-
ment) interface which effectively connects the DTE to a
MAU. The differential interface provided by the
Am79C971 controller is fully compliant to Section 7 of
ISO 8802-3 (ANSI/IEEE 802.3) standard.
After the Am79C971 controller initiates a transmission
it will expect to see data
“
looped-back
”
on the DI
±
pair
(when the AUI port is selected). This will internally gen-
erate a
“
carrier sense,
”
indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This
“
carrier sense
”
signal
must be asserted before end of transmission. If
“
carrier
sense
”
does not become active in response to the data
transmission, or becomes inactive before the end of
transmission, the loss of carrier (LCAR) error bit will be
set in the transmit descriptor ring (TMD2, bit 27) after
the frame has been transmitted.
Differential Input Termination
The differential input for the Manchester data (DI
±
) is
externally terminated by two 40.2-
resistors and one
optional common-mode bypass capacitor, as shown in
Figure 36. The differential input impedance, Z
IDF
, and
the common-mode input impedance, Z
ICM
, are speci-
fied so that the Ethernet specification for cable termina-
tion impedance is met using standard 1% resistor
terminators. If SIP devices are used, 39 ohms is also a
suitable value. The CI
±
differential inputs are termi-
nated in exactly the same way as the DI
±
pair.
Figure 36.
AUI Differential Input Termination
Collision Detection
A MAU detects the collision condition on the network
and generates a 10-MHz differential signal at the CI
±
inputs. This collision signal passes through an input
stage which detects signal levels and pulse duration.
When the signal is detected by the MENDEC, it sets the
ICLSN line HIGH. The condition continues for approxi-
mately 1.5 bit times after the last LOW-to-HIGH transi-
tion on CI
±
.
Twisted-Pair Transceiver
This section describes operation of the Twisted-Pair
Transceiver (T-MAU) when operating in half-duplex
mode. When in half-duplex mode, the T-MAU imple-
ments the MAU functions for the Twisted Pair Medium
as specified by the supplement to the IEEE 802.3 stan-
dard (Type 10BASE-T). When operating in full-duplex
mode, the MAC engine behavior changes as described
in the section
Full-Duplex Operation
.
The T-MAU provides twisted pair driver and receiver cir-
cuits, including on-board transmit digital predistortion
and receiver squelch, and a number of additional fea-
tures including Link Status indication, Automatic
Twisted Pair Receive Polarity Detection/Correction and
Indication, Receive Carrier Sense, Transmit Active, and
Collision Present indication.
Twisted Pair Transmit Function
The differential driver circuitry in the TXD
±
and TXP
±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted Pair cable, as specified
by the 10BASE-T supplement to the ISO 8802-3 (IEEE/
Am79C971
DI+
DI-
40.2
40.2
0.01
μ
F
to
0.1
μ
F
AUI Isolation
Transformer
20550D-39
相關(guān)PDF資料 |
PDF描述 |
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| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972 | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C971AKC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C971AVC | 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays |
| AM79C971AVC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AVC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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