參數(shù)資料
型號(hào)： AM79C971
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述： PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線
文件頁(yè)數(shù)： 118/265頁(yè)
文件大?。?/td> 3190K
代理商： AM79C971
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118
Am79C971
by H_RESET, S_RESET, or by
setting the STOP bit.
CSR1: Initialization Block Address 0
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADR[15:0]
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tions 1 and 0 must both be 0 to
align the initialization block to a
DWord boundary.
This register is aliased with
CSR16.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET
or S_RESET, or by setting the
STOP bit.
CSR2: Initialization Block Address 1
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
However, if SSIZE32 is reset
(BCR20,
bit
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32-bit address bus.
Note that the 16-bit software
structures
specified
SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C971 bus master access-
es, while the 32-bit hardware for
which the Am79C971 controller is
intended will require 32 bits of ad-
dress.
Therefore,
SSIZE32 = 0, the IADR[31:24]
bits will be appended to the 24-bit
initialization address, to each 24-
bit descriptor base address and
to each beginning 24-bit buffer
address in order to form complete
32-bit addresses. The upper 8
bits that exist in the descriptor ad-
8),
then
the
by
the
whenever
dress registers and the buffer ad-
dress registers which are stored
on board the Am79C971 control-
ler will be overwritten with the
IADR[31:24] value, so that CSR
accesses to these registers will
show the 32-bit address that in-
cludes the appended field.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures - i.e., descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
7-0
IADR[23:16] Bits 23 through 16 of the address
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2
’
s
contents.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
CSR3: Interrupt Masks and Deferral Control
Bit
31-16
Name
RES
Description
Reserved locations. Written as
zeros and read as undefined.
15
RES
Reserved location. Read and
written as zero.
14
BABLM
Babble Mask. If BABLM is set,
the BABL bit will be masked and
unable to set the INTR bit.
Read/Write accessible always.
BABLM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
相關(guān)PDF資料
PDF描述
AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
AM79C972BKCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C971AKC 制造商:Advanced Micro Devices 功能描述:
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AM79C971AVC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C971AWW WAF 制造商:Advanced Micro Devices 功能描述:
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