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參數(shù)資料
| 型號(hào)： | AM79C971 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnet⑩快速單芯片全雙工10/100 Mbps以太網(wǎng)控制器，PCI總線 |
| 文件頁數(shù)： | 122/265頁 |
| 文件大?。?/td> | 3190K |
| 代理商： | AM79C971 |
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122
Am79C971
10
ASTRP_RCV Auto Strip Receive. When set,
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
Read/Write accessible always.
ASTRP_RCV
is
H_RESET or S_RESET and is
unaffected by the STOP bit.
cleared
by
9
MFCO
Missed Frame Counter Overflow
is set by the Am79C971 control-
ler when the Missed Frame
Counter (CSR112 and CSR114)
has wrapped around.
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
Read/Write accessible always.
MFCO is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
MFCO
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
8
MFCOM
Missed Frame Counter Overflow
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
Read/Write accessible always.
MFCOM is set to 1 by H_RESET
or S_RESET and is not affected
by the STOP bit.
7
UINTCMD
User
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1.
UINTCMD will be cleared inter-
nally after the Am79C971 control-
ler has set UINT to 1.
Interrupt
Command.
Read/Write accessible always.
UINTCMD
is
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
6
UINT
User Interrupt. UINT is set by the
Am79C971 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Read/Write accessible always.
UINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
UINT
is
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
5
RCVCCO
Receive Collision Counter Over-
flow is set by the Am79C971 con-
troller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a 1. Writing a 0 has no
effect. RCVCCO is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
4
RCVCCOM Receive Collision Counter Over-
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RCVCCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
3
TXSTRT
Transmit Start status is set by the
Am79C971 controller whenever it
begins transmission of a frame.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. TXSTRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
2
TXSTRTM
Transmit Start Mask. If TX-
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Read/Write accessible always.
TXSTRTM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972 | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C971AKC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C971AVC | 制造商:Advanced Micro Devices 功能描述:10/100 MBPS ETHERNET - Trays |
| AM79C971AVC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AVC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C971AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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