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參數(shù)資料
| 型號(hào)： | ADUC834BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數(shù)： | 68/72頁 |
| 文件大?。?/td> | 1451K |
| 代理商： | ADUC834BS |
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(12 March 2002) REV.
P
rC
ADuC834
–
68
–
PRELIMINARY TECHNICAL DATA
should be noted that the SPI power down interrupt enable bit
(SERIPD) in the PCON SFR must first be set to allow this
mode of operation.
INT 0
Interrupt
Power-down mode is terminated and the CPU services the
INT 0
interrupt. T he RET I at the end of the ISR will return the
core to the instruction after that which enabled power-down. It
should be noted that the
INT 0
power-down interrupt enable bit
(INT 0PD) in the PCON SFR must first be set to allow this
mode of operation.
Grounding and Board Layout Recommendations
As with all high resolution data converters, special attention must
be paid to grounding and PC board layout of ADuC834-based
designs in order to achieve optimum performance from the ADCs
and DAC.
Although the ADuC834 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are con-
nected together very close to the ADuC834, as illustrated in the
simplified example of Figure 59a. In systems where digital and
analog ground planes are connected together somewhere else
(at the system
’
s power supply for example), they cannot be con-
nected again near the ADuC834 since a ground loop would result.
In these cases, tie the ADuC834
’
s AGND and DGND pins all
to the analog ground plane, as illustrated in Figure 59b. In systems
with only one ground plane, ensure that the digital and analog
components are physically separated onto separate halves of the
board such that digital return currents do not flow near analog
circuitry and vice versa. T he ADuC834 can then be placed between
the digital and analog sections, as illustrated in Figure 59c.
DGND
PLACE ANALOG COM-
PONENTS HERE
A
B
C
AGND
DGND
AGND
PLACE DIGITAL
COMPONENTS HERE
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS
HERE
GND
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL COM-
PONENTS
HERE
Figure 59. System Grounding Schemes
In all of these scenarios, and in more complicated real-life appli-
cations, keep in mind the flow of current from the supplies and
back to ground. Make sure the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. For example, do not power components
on the analog side of Figure 59b with DV
DD
since that
would force return currents from DV
DD
to flow through
AGND. Also, try to avoid digital currents flowing under analog
circuitry, which could happen if the user placed a noisy digi-
tal chip on the left half of the board in Figure 59c.
Whenever possible, avoid large discontinuities in the ground
plane(s) (such as are formed by a long trace on the same
layer), since they force return signals to travel a longer path.
And of course, make all connections to the ground plane di-
rectly, with little or no trace separating the pin from its via to
ground.
If the user plans to connect fast logic signals (rise/fall time <
5 ns) to any of the ADuC834
’
s digital inputs, add a series
resistor to each relevant line to keep rise and fall times longer
than 5 ns at the ADuC834 input pins. A value of 100
or 200
is usually sufficient to prevent high-speed signals from coupling
capacitively into the ADuC834 and affecting the accuracy of
ADC conversions.
ADuC834 System Self-Identification
In some hardware designs it may be an advantage for the
software running on the ADuC834 target to identify the host
MicroConverter. For example, code running on the ADuC834
may also be used with the ADuC824 or the ADuC816 but is
required to operate differently.
T he CHIPID SFR is a read-only register located at SFR ad-
dress C2 hex. T he upper nibble of this SFR is set to 2X hex
to designate an ADuC834.
Clock Oscillator
As described earlier, the core clock frequency for the
ADuC834 is generated from an on-chip PL L that locks onto
a multiple (384 times) of 32.768 kHz. T he latter is generated
from an internal clock oscillator. T o use the internal clock
oscillator, connect a 32.768 kHz parallel resonant crystal
between X T AL 1 and X T AL2 pins (32 and 33) as shown in
Figure 60.
As shown in the typical external crystal connection diagram
in Figure 60, two internal 12 pF capacitors are provided on-chip.
T hese are connected internally, directly to the X T AL 1 and
X T AL2 pins and the total input capacitances at both pins is
detailed in the specification section of this data sheet. T he
value of the total load capacitance required for the external crystal
should be the value recommended by the crystal manufacturer
for use with that specific crystal. In many cases, because of the
on-chip capacitors, additional external load capacitors will not be
required.
XTAL2
XTAL1
32.768kHz
TO INTERNAL
PLL
ADuC834
12pF
12pF
Figure 60. External Parallel Resonant Crystal Connections
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