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參數(shù)資料
| 型號(hào)： | ADUC834BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁(yè)數(shù)： | 46/72頁(yè) |
| 文件大小： | 1451K |
| 代理商： | ADUC834BS |
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(12 March 2002) REV.
P
rC
ADuC834
–
46
–
PRELIMINARY TECHNICAL DATA
PL L C ON
SFR Address
Power-On Default Value
Bit Addressable
PL L C ontrol Register
D7H
03H
No
T able X VII. PLLCON SFR Bit Designations
Bit
Name
Description
7
OSC_PD
Oscillator Power-down Bit.
Set
by user to halt the 32 kHz oscillator in power-down mode.
Cleared
by user to enable the 32 kHz oscillator in power-down mode.
T his feature allows the T IC to continue counting even in power-down mode.
PLL Lock Bit.
T his is a read only bit.
Set
automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the
external crystal becomes subsequently disconnected the PLL will rail and the core will halt.
Cleared
automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.
T his may be due to the absence of a crystal clock or an external crystal at power-on. In this mode,
the PLL output can be 12.58 MHz ± 20%.
Reserved for future use; should be written with
‘
0.
’
Reading this bit returns the state of the external
EA
pin latched at reset or power-on.
Fast Interrupt Response Bit.
Set
by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
regardless of the configuration of the CD2
–
0 bits (see below). After user code has returned from an
interrupt, the core resumes code execution at the core clock selected by the CD2
–
0 bits.
Cleared
by user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
T his number determines the frequency at which the microcontroller core will operate.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
0
0
12.582912
0
0
1
6.291456
0
1
0
3.145728
0
1
1
1.572864 (Default Core Clock Frequency)
1
0
0
0.786432
1
0
1
0.393216
1
1
0
0.196608
1
1
1
0.098304
6
LOCK
5
4
3
---
LT EA
FINT
2
1
0
CD2
CD1
CD0
ON-CHIP PLL
T he ADuC834 is intended for use with a 32.768 kHz watch
crystal. A PLL locks onto a multiple (384) of this to provide a
stable 12.582912 MHz clock for the system. T he core can
operate at this frequency or at binary submultiples of it to
allow power saving in cases where maximum core perfor-
mance is not required. T he default core clock is the PL L
clock divided by 8 or 1.572864 MHz. T he ADC clocks are also
derived from the PLL clock, with the modulator rate being the
same as the crystal oscillator frequency. T he above choice of
frequencies ensures that the modulators and the core will be
synchronous, regardless of the core clock rate. T he PL L con-
trol register is PLLCON.
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