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參數(shù)資料
| 型號： | ADUC834BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數(shù)： | 52/72頁 |
| 文件大小： | 1451K |
| 代理商： | ADUC834BS |
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(12 March 2002) REV.
P
rC
ADuC834
–
52
–
PRELIMINARY TECHNICAL DATA
SPIDAT
Function
SPI Data Register
T he SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user
code to read data just received by the SPI interface.
F7H
00H
No
SFR Address
Power-On Default Value
Bit Addressable
Using the SPI Interface
Depending on the configuration of the bits in the SPICON
SFR shown in T able X X I, the ADuC834 SPI interface will
transmit or receive data in a number of possible modes. Figure
43 shows all possible ADuC834 SPI configurations and the tim-
ing relationships and synchronization between the signals
involved. Also shown in this figure is the SPI interrupt bit
(ISPI) and how it is triggered at the end of each byte-wide commu-
nication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
S S
Figure 43. ADuC834, SPI Timing, All Modes
SPI Interface
—
Master Mode
In master mode, the SCLOCK pin is always an output and gener-
ates a burst of eight clocks whenever user code writes to the
SPIDAT register. T he SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS
pin is not used in master mode. If the ADuC834 needs to
assert the
SS
pin on an external slave device, a Port digital output
pin should be used.
In master mode a byte transmission or reception is initiated
by a write to SPIDAT . Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period a data bit is also sampled via MISO.
After eight clocks, the transmitted byte will have been completely
transmitted and the input byte will be waiting in the input shift
register. T he ISPI flag will be set automatically and an interrupt
will occur if enabled. T he value in the shift register will be
latched into SPIDAT .
SPI Interface
—
Slave Mode
In slave mode the SC L OC K is an input. T he
SS
pin must
also be driven low externally during the byte communication.
T ransmission is also initiated by a write to SPIDAT . In slave
mode, a data bit is transmitted via MISO and a data bit is received
via MOSI through each input SCLOCK period. After eight
clocks, the transmitted byte will have been completely transmitted
and the input byte will be waiting in the input shift register. T he
ISPI flag will be set automatically and an interrupt will occur
if enabled. T he value in the shift register will be latched into
SPIDAT only when the transmission/reception of a byte has
been completed. T he end of transmission occurs after the
eighth clock has been received, if CPHA = 1 or when
SS
re-
turns high if CPHA = 0.
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