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參數(shù)資料
| 型號： | ADUC834BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數(shù)： | 57/72頁 |
| 文件大?。?/td> | 1451K |
| 代理商： | ADUC834BS |
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REV.
P
rC (12 March 2002)
ADuC834
–
57
–
PRELIMINARY TECHNICAL DATA
T IME R/C OUNT E R 0 AND 1 OPE RAT ING MOD E S
T he following paragraphs describe the operating modes for
timer/counters 0 and 1. Unless otherwise noted, it should be
assumed that these modes of operation are the same for timer 0 as
for timer 1.
Mode 0 (13-Bit T imer/C ounter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32 pre-
scaler. Figure 44 shows mode 0 operation.
12
CORE
CLK
*
CONTROL
P3.4/T0
GATE
P3.2/
INT0
TR0
TF0
TL0
(5 BITS)
TH0
(8 BITS)
INTERRUPT
C/
T
= 0
C/
T
= 1
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 44. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit regis-
ter. As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag T F0. T he overflow flag, T F0, can then be used to
request an interrupt. T he counted input is enabled to the timer
when T R0 = 1 and either Gate = 0 or
INT 0
= 1. Setting Gate = 1
allows the timer to be controlled by external input
INT 0
, to
facilitate pulsewidth measurements. T R0 is a control bit in the
special function register T CON; Gate is in T MOD. T he 13-bit
register consists of all eight bits of T H0 and the lower five bits of
T L0. T he upper three bits of T L0 are indeterminate and should
be ignored. Setting the run flag (T R0) does not clear the regis-
ters.
Mode 1 (16-Bit T imer/C ounter)
Mode 1 is the same as Mode 0, except that the timer register
is running with all 16 bits. Mode 1 is shown in Figure 45.
12
CORE
CLK
*
CONTROL
P3.4/T0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
C/
T
= 0
C/
T
= 1
GATE
P3.2/
INT0
TR0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 45. Timer/Counter 0, Mode 1
Mode 2 (8-Bit T imer/C ounter with Auto Reload)
Mode 2 configures the timer register as an 8-bit counter (T L0)
with automatic reload, as shown in Figure 46. Overflow from T L0
not only sets T F0, but also reloads T L0 with the contents of T H0,
which is preset by software. T he reload leaves T H0 unchanged.
12
CORE
CLK
*
CONTROL
P3.4/T0
TF0
TL0
(8 BITS)
INTERRUPT
C/
T
= 0
C/
T
= 1
RELOAD
TH0
(8 BITS)
GATE
P3.2/
INT0
TR0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 46. Timer/Counter 0, Mode 2
Mode 3 (T wo 8-Bit T imer/C ounters)
Mode 3 has different effects on timer 0 and timer 1. T imer 1 in
Mode 3 simply holds its count. T he effect is the same as setting
T R1 = 0. T imer 0 in Mode 3 establishes T L0 and T H0 as two
separate counters. T his configuration is shown in Figure 47. T L0
uses the timer 0 control bits: C/T , Gate, T R0,
INT 0
, and T F0.
T H0 is locked into a timer function (counting machine cycles)
and takes over the use of T R1 and T F1 from timer 1. T hus, T H0
now controls the
“
timer 1
”
interrupt. Mode 3 is provided for
applications requiring an extra 8-bit timer or counter.
When timer 0 is in Mode 3, timer 1 can be turned on and off by
switching it out of, and into, its own Mode 3, or can still be used by
the serial interface as a Baud Rate Generator. In fact, it can be used,
in any application not requiring an interrupt from timer 1 itself.
12
CORE
CLK
*
TL0
(8 BITS)
TF0
INTERRUPT
CONTROL
P3.4/T0
C/
T
= 0
C/
T
= 1
TH0
(8 BITS)
TF1
INTERRUPT
CORE
CLK/12
TR1
CORE
CLK/12
CONTROL
GATE
P3.2/
INT0
TR0
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 47. Timer/Counter 0, Mode 3
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