參數(shù)資料
型號: ADUC834BS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝: 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁數(shù): 44/72頁
文件大小: 1451K
代理商: ADUC834BS
(12 March 2002) REV.
P
rC
ADuC834
44
PRELIMINARY TECHNICAL DATA
PWM MODE S OF OPE RAT ION
MODE 0: PWM disblabled
T he PWM is disabled allowing P1.0 and P1.1 be used as nor-
mal.
MODE 1: Single Variable resolution PWM
In this mode both the pulse length and the cycle time (pe-
riod) are programmable in user code allowing the resolution
of the PWM to be variable.
PWM1H/L sets the period of the output waveform. Setting
PWM1H/L to 65536 gives a 16-bit PWM with a maximum
output rate of 192Hz (12.583MHz/65536). Setting
PWM1H/L to 4096 gives a 12-bit PWM with a maximum
output rate of 3072Hz (12.583MHz/4096).Reducing
PWM1H/L reduces the resolution but increases the maxi-
mum output rate of the PWM.
PWM0H/L sets the width of the output waveform as shown
in the diagram below.
P1.0
PWM COUNTER
PWM1H/L
0
PWM0H/L
Figure 36. ADuC834 PWM in Mode 1
MODE 2: T win 8-bit PWM
In this mode both the pulse and cycle time (period) are pro-
grammable however the maximum resolution of the PWM
output is 8-bits.
PWM1L sets the period for both PWM outputs. T ypically this
will be set to 255 (FFh) to give an 8-bit PWM although it is
possible to reduce this as necessary. A value of 100 is loaded
here to give a percentage PWM (i.e. the PWM is accurate to
1%).
T he ouputs of the PWM at P1.0 and P1.1 are shown in the
diagram below. As can be seen the output of PWM0 (P1.0)
goes low when the PWM counter equals PWM0L. T he output
of PWM1 (P1.1) goes high when the PWM counter equals
PWM1H and goes low again when the PWM counter equals
PWM0H. Often PWM1H will be set to 0 so that both outputs
start simultaneously.
P1.1
P1.0
PWM COUNTER
PWM1H
0
PWM1L
PWM0H
PWM0L
Figure 37. PWM Mode 2
MODE 3: T win 16-bit PWM
In this mode the pulse is programmable but the cycle time
(period) is fixed. T he PWM counter is fixed to count from 0
to 65536 giving a fixed 16-bit resolution. T his means that
the maximum output of the PWM is 192Hz.
As shown below while the PWM counter is less than
PWM0H/L then the output of PWM0 (P1.0) is high. Once
the PWM counter equals PWM0H/L then PWM0 (P1.0)
goes low and remains low until the PWM counter is rolls
over.
Similarly while the PWM counter is less than PWM1H/L
then the output of PWM1 (P1.1) is high. Once the PWM
counter equals PWM1H/L then PWM1 (P1.1) goes low and
remains low until the PWM counter is rolls over.
In this mode PWMs must be synchronised. i.e. Both PWM0
(P1.0) and PWM1 (P1.1) go high at the same time.
P1.1
P1.0
PWM COUNTER
PWM1H/L
0
65536
PWM0H/L
Figure 38. PWM Mode 3
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