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參數(shù)資料
| 型號： | ADUC834BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數(shù)： | 67/72頁 |
| 文件大?。?/td> | 1451K |
| 代理商： | ADUC834BS |
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REV.
P
rC (12 March 2002)
ADuC834
–
67
–
PRELIMINARY TECHNICAL DATA
Power Supplies
T he ADuC834
’
s operational power supply voltage range is
2.7 V to 5.25 V. Although the guaranteed data sheet specifica-
tions are given only for power supplies within 2.7 V to 3.6 V or
+5% of the nominal 5 V level, the chip will function equally
well at any power supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AV
DD
and
DV
DD
respectively) allow AV
DD
to be kept relatively free of
noisy digital signals often present on the system DVDD line. In
this mode the part can also operate with split supplies; that is,
using different voltage supply levels for each supply. For ex-
ample, this means that the system can be designed to operate
with a DV
DD
voltage level of 3 V while the AV
DD
level can be at
5 V or vice-versa if required. A typical split supply configuration
is show in Figure 57.
DV
DD
48
34
20
ADuC834
5
6
AGND
AV
DD
+
0.1 F
10 F
ANALOG SUPPLY
10 F
DGND
35
21
47
0.1 F
+
DIGITAL SUPPLY
Figure 57. External Dual Supply Connections
As an alternative to providing two separate power supplies,
AV
DD
can be kept quiet by placing a small series resistor and/or
ferrite bead between it and DV
DD
, and then decoupling AV
DD
separately to ground. An example of this configuration is shown
in Figure 58. With this configuration other analog circuitry
(such as op-amps, voltage reference, etc.) can be powered from
the AV
DD
supply line as well.
DV
DD
48
34
20
ADuC834
5
6
AGND
AV
DD
0.1 F
10 F
DGND
35
21
47
0.1 F
+
DIGITAL SUPPLY
10 F
1.6
BEAD
Figure 58. External Single Supply Connections
Notice that in both Figure 57 and Figure 58, a large value (10 μF)
reservoir capacitor sits on DV
DD
and a separate 10 μF capacitor
sits on AV
DD
. Also, local small-value (0.1 μF) capacitors are
located at each VDD pin of the chip. As per standard design prac-
tice, be sure to include all of these capacitors, and ensure
the smaller capacitors are closest to each AV
DD
pin with trace
lengths as short as possible. Connect the ground terminal of each
of these capacitors directly to the underlying ground plane.
Finally, it should also be noticed that, at all times, the analog
and digital ground pins on the ADuC834 should be referenced
to the same system ground reference point.
Power-On Reset Operation
An internal POR (power-on reset) is implemented on the
ADuC834. For DV
DD
below 2.63V the internal POR will hold the
ADuC834 in reset. As DV
DD
rises above 2.63V an internal timer
will timeout for approx 128ms before the part is released from
reset. T he user must ensure that the power supply must have
reached at least a 2.7 V level by this time.
Power C onsumption
T he
“
CORE
”
values given on the spec pages represent the cur-
rent drawn by DV
DD
, while the rest (
“
ADC
”
, and
“
DAC
”
) are
pulled by the AV
DD
pin and can be disabled in software when
not in use. T he other on-chip peripherals (watchdog timer,
power supply monitor, etc.) consume negligible current and are
therefore lumped in with the
“
CORE
”
operating current here.
Of course, the user must add any currents sourced by the paral-
lel and serial I/O pins, and that sourced by the DAC , in order
to determine the total current needed at the ADuC834
’
s sup-
ply pins. Also, current draw from the DV
DD
supply will increase
by approximately 5 mA during Flash/EE erase and program
cycles
Power-Saving Modes
Setting the Idle and Power-Down Mode bits, PCON.0 and
PC ON.1 respectively, in the PCON SFR described in T able II,
allows the chip to be switched from normal mode into idle mode,
and also into full power-down mode.
In idle mode, the oscillator continues to run, but the core clock
generated from the PLL is halted. T he on-chip peripherals con-
tinue to receive the clock, and remain functional. T he CPU status
is preserved with the stack pointer, program counter, and all other
internal registers maintain their data during idle mode. Port
pins and DAC output pins also retain their states, and ALE and
PSEN
outputs go high in this mode. T he chip will recover from
idle mode upon receiving any enabled interrupt, or on receiving
a hardware reset.
In power-down mode, both the PLL and the clock to the core
are stopped. T he on-chip oscillator can be halted or can continue
to oscillate depending on the state of the oscillator power-down
bit (OSC _PD) in the PL L C ON SFR. T he T IC , being driven
directly from the oscillator, can also be enabled during power-
down. All other on-chip peripherals however, are shut down.
Port pins retain their logic levels in this mode, but the DAC output
goes to a high-impedance state (three-state) while AL E and
PSEN
outputs are held low. During full power-down mode,
the ADuC834 typically consumes a total of 15 μA. T here are
five ways of terminating power-down mode:
Asserting the RE SE T pin (#15)
Returns to normal mode all registers are set to their default state
and program execution starts at the reset vector once the Reset
pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128ms later.
T ime Interval Counter (T IC) Interrupt
Power-down mode is terminated and the CPU services the T IC
interrupt. T he RET I at the end of the T IC ISR will return the
core to the instruction after that which enabled power down.
SPI Interrupt
Power-down mode is terminated and the CPU services the SPI
interrupt. T he RET I at the end of the ISR will return the core
to the instruction after that which enabled power down. It
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