參數(shù)資料
型號: ADUC834BS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝: 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁數(shù): 58/72頁
文件大?。?/td> 1451K
代理商: ADUC834BS
(12 March 2002) REV.
P
rC
ADuC834
58
PRELIMINARY TECHNICAL DATA
T IME R/COUNT E R 2 OPE RAT ING MODE S
T he following paragraphs describe the operating modes for
timer/counter 2. T he operating modes are selected by bits in the
T 2CON SFR as shown in T able X X IX .
T able X X VIII. T imer 2 Operating modes
RCLK (or) T CLK
CAP2
T R2
MODE
0
0
1
X
0
1
X
X
1
1
1
0
16-Bit Autoreload
16-Bit Capture
Baud Rate
OFF
16-Bit Autoreload Mode
In
Autoreload
mode, there are two options, which are selected
by bit EX EN2 in T 2CON. If EX EN2 = 0, then when T imer 2
rolls over it not only sets T F2 but also causes the T imer 2 registers
to be reloaded with the 16-bit value in registers RC AP2L and
RC AP2H, which are preset by software. If EX EN2 = 1, then
T imer 2 still performs the above, but with the added feature that
a 1-to-0 transition at external input T 2EX will also trigger the
16-bit reload and set EX F2. T he autoreload mode is illustrated
in Figure 48 below.
CORE
CLK
*
12
T2
PIN
C/
T 2
= 0
C/
T 2
= 1
TR2
CONTROL
TL2
(8-BITS)
TH2
(8-BITS)
RELOAD
TF2
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L
RCAP2H
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 48. Timer/Counter 2, 16-Bit Autoreload Mode
TF2
CORE
CLK
*
12
T2
PIN
TR2
CONTROL
TL2
(8-BITS)
TH2
(8-BITS)
CAPTURE
EXF2
TIMER
INTERRUPT
EXEN2
CONTROL
TRANSITION
DETECTOR
T2EX
PIN
RCAP2L
RCAP2H
C/
T 2
= 0
C/
T 2
= 1
*
THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 46
Figure 49. Timer/Counter 2, 16-Bit Capture Mode
16-Bit C apture Mode
In the
Capture
mode, there are again two options, which are
selected by bit EX EN2 in T 2CON. If EX EN2 = 0, then T imer 2
is a 16-bit timer or counter which, upon overflowing, sets bit T F2,
the T imer 2 overflow bit, which can be used to generate an inter-
rupt. If EX EN2 = 1, then T imer 2 still performs the above, but
a l-to-0 transition on external input T 2EX causes the current value
in the T imer 2 registers, T L2 and T H2, to be captured into regis-
ters RC AP2L and RC AP2H, respectively. In addition, the
transition at T 2EX causes bit EX F2 in T 2CON to be set, and
EX F2, like T F2, can generate an interrupt. T he Capture Mode
is illustrated in Figure 49.
T he baud rate generator mode is selected by RCLK = 1 and/or
T C L K = 1.
In either case if T imer 2 is being used to generate the baud rate,
the T F2 interrupt flag will not occur. Hence T imer 2 interrupts
will not occur so they do not have to be disabled. In this mode
the EX F2 flag, however, can still cause interrupts and this can
be used as a third external interrupt.
Baud rate generation will be described as part of the UART
serial port operation in the following pages.
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