參數(shù)資料
型號(hào)： ADUC834BS
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝： 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁數(shù)： 45/72頁
文件大?。?/td> 1451K
代理商： ADUC834BS
REV.
P
rC (12 March 2002)
ADuC834
–
45
–
PRELIMINARY TECHNICAL DATA
MODE 4: Dual NRZ 16-bit
Σ
DAC
Mode 4 provides a high speed PWM output similar to that of a
Σ
DAC. T ypically this mode will be used with the 12.58MHz
clock.
In this mode P1.0 and P1.1 are updated every PWM clock
(80ns in the case of 12.58MHz). Over any 65536 cycles (16 bit
PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for
65536 - PWM0H/L. Similarly PWM1 (P1.1) is high for
PWM1H/L cycles during this same time.
For lower resolution, higher speed DAC outputs write 0
’
s to
the LSBs that are not required. If for example only 12 bit per-
formance is required then write 0
’
s to the 4LSBs. T his means
that 12 bit accuracy in the PWM output can occur at 3kHz.
Similary writing 0
’
s to the 8LSBs gives 8 bit accuracy at 49kHz.
e.g. if PWM0H was set to 4010H (slightly above one quater of
FS) then typically P1.0 will be low for three clocks and high for
one clock (each clock is 80ns appox). Over every 65536 clocks
the PWM will compromise for the fact that the output should
be slightly above one quater of fullscale by leaving the output
high for two clocks in four every so often.
+
LATCH
PWM0H/L
12.583MHz
16 BIT
0, ,
‰
,
…
, 0
80us
0
0
1
1
1
1
1
80us
0
1
0
0
0
0
0
16 BIT
16 BIT
16 BIT
16 BIT
16 BIT
0, ,
‰
,
…
, 0
CARRY OUT AT P1.0
CARRY OUT AT P1.1
…
PWM1H/L
Figure 39. PWM Mode 4
MODE 5: Dual 8-bit PWM
In this mode both the pulse and cycle time (period) are inde-
pendently programmable by using the high and low bytes of the
PWM counters independently. T he output resolution and
period are set by the PWM1L and PWM1H registers for the
P1.0 and P1.1 outputs respectively. PWM0L and PWM0H will
set the width of the high pulse for the P1.0 and P1.1 outputs
respectively. Both channels have same clock source and clock
divider.
P1.1
P1.0
PWM COUNTERS
PWM1H
0
PWM1L
PWM0H
PWM0L
Figure 40. PWM Mode 5
MODE 6: Dual RZ 16-bit
Σ
DAC
Mode 6 provides the exact same functionality as mode 4
except that in this mode the PWM output is ANDed with
the PWM clock. i.e. every output 1 is only high for half a
clock and low for the other half clock. T his return to zero
(RZ) mode reduces any errors due to mismatch between rise
time and fall time of the PWM outputs and is recommended
over mode 4 for accurate PWM outputs.
T he disadvantage of this mode is that the dynamic range of
the PWM output is halved from 0->DV
DD
to 0->DV
DD
/2.
e.g. if PWM0H was set to 4010H (slightly above one quater
of FS) then typically P1.0 will be low for three full clocks (3
x 80ns), high for half a clock (40ns) and then low again for
half a clock (40ns) before repeating itself. Over every 65536
clocks the PWM will compromise for the fact that the out-
put should be slightly above one quater of fullscale by
leaving the output high for two half clocks in four every so
often.
+
LATCH
PWM0H/L
12.583MHz
16 BIT
0, ,
‰
,
…
, 0
80us
0
0
1
1
1
1
1
80us
0
1
0
0
0
0
0
16 BIT
16 BIT
16 BIT
16 BIT
16 BIT
0, ,
‰
,
…
, 0
CARRY OUT AT P1.0
CARRY OUT AT P1.1
…
PWM1H/L
Figure 41. PWM Mode 6
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