參數(shù)資料
型號(hào): ADUC834BS
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52
封裝: 14 X 14 MM, MO-022-AC-1, MQFP-52
文件頁(yè)數(shù): 23/72頁(yè)
文件大?。?/td> 1451K
代理商: ADUC834BS
REV.
P
rC (12 March 2002)
ADuC834
23
PRELIMINARY TECHNICAL DATA
Data Pointer (DPT R)
T he Data Pointer is made up of three 8-bit registers, named
DPP (page byte), DPH (high byte) and DPL (low byte).
T hese are used to provide memory addresses for internal and
external code access and external data access. It may be ma-
nipulated as a 16-bit register (DPT R = DPH, DPL), although
INC DPT R instructions will automatically carry over to DPP,
or as three independent 8-bit registers (DPP, DPH, DPL).
T he ADuC834 supports dual data pointers. Refer to the Dual
Data Pointer section later in this datasheet.
Program Status Word (PSW)
T he PSW SFR contains several bits reflecting the current status
of the CPU as detailed in T able I.
SFR Address
Power ON Default Value
Bit Addressable
D0H
00H
Yes
T able I. PSW SFR Bit Designations
Bit
Name
Description
7
6
5
4
3
CY
AC
F0
RS1
RS0
Carry Flag
Auxiliary Carry Flag
General-Purpose Flag
Register Bank Select Bits
RS1
RS0
0
0
0
1
1
0
1
1
Overflow Flag
General-Purpose Flag
Parity Bit
Selected Bank
0
1
2
3
2
1
0
OV
F1
P
Power Control SFR (PCON)
T he PCON SFR contains bits for power-saving options and
general-purpose status flags as shown in T able II.
SFR Address
Power ON Default Value
Bit Addressable
87H
00H
No
T able II. PCON SFR Bit Designations
Bit
Name
Description
7
6
SMOD
SERIPD
Double UART Baud Rate
SPI Power-Down Interrupt
Enable
INT 0
Power-Down Interrupt
Enable
Disable ALE Output
General-Purpose Flag Bit
General-Purpose Flag Bit
Power-Down Mode Enable
Idle Mode Enable
5
INT 0PD
4
3
2
1
0
ALEOFF
GF1
GF0
PD
IDL
ADuC834 Configuration SFR (CFG834)
T he CFG834 SFR contains the necessary bits to configure the
internal X RAM and the extended SP. By default it configures
the user into 8051 mode. i.e. extended SP is disabled, internal
X RAM is disabled.
SFR Address
Power ON Default Value
Bit Addressable
AFhH
00H
No
T able III. CFG834 SFR Bit Designations
Bit
Name
Description
7
EX SP
Extended SP Enable
If this bit is set then the stack will
rollover from SPH/SP = 00FFh to
0100h.
If this bit is clear then the SPH SFR
will be disabled and the stack will
rollover from SP=FFh to SP =00h
----
----
----
----
----
----
X RAM Enable Bit
If this bit is set then the internal
X RAM will be mapped into the lower
2kBytes of the external address space.
If this bit is clear then the internal
X RAM will not be accessible and the
external data memory will be mapped
into the lower 2kBytes of external data
memory. (see fig 14)
6
5
4
3
2
1
0
----
----
----
----
----
----
X RAMEN
.
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