
REV.
P
rC (12 March 2002)
ADuC834
–
37
–
PRELIMINARY TECHNICAL DATA
NONVOLAT ILE FLASH/E E ME MORY
Flash/E E Memory Overview
T he ADuC834 incorporates Flash/EE memory technology on-
chip to provide the user with nonvolatile, in-circuit
reprogrammable, code and data memory space.
Flash/EE memory is a relatively recent type of nonvolatile
memory technology and is based on a single transistor cell
architecture.
T his technology is basically an outgrowth of EPROM technology
and was developed through the late 1980s. Flash/EE memory
takes the flexible in-circuit reprogrammable features of
EEPROM and combines them with the space efficient/density
features of EPROM (see Figure 25).
Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be
implemented to achieve the space efficiencies or memory
densities required by a given design.
Like EEPROM, Flash memory can be programmed in-system
at a byte level, although it must first be erased; the erase being
performed in page blocks. T hus, Flash memory is often and
more correctly referred to as Flash/EE memory.
FLASH/EE MEMORY
TECHNOLOGY
SPACE EFFICIENT/
DENSITY
IN-CIRCUIT
REPROGRAMMABLE
EPROM
TECHNOLOGY
EEPROM
TECHNOLOGY
Figure 25. Flash/EE Memory Development
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density and low cost. Incorporated in the
ADuC834, Flash/EE memory technology allows the user to
update program code space in-circuit, without the need to
replace one-time programmable (OT P) devices at remote
operating nodes.
Flash/E E Memory and the ADuC834
T he ADuC834 provides two arrays of Flash/EE memory for user
applications. 62kBytes of Flash/EE Program space are pro-
vided on-chip to facilitate code execution without any external
discrete ROM device requirements. T he program memory can
be programmed in-circuit, using the serial download mode
provided, using conventional third party memory programmers
or via a user defined protocol who can configure it as data if
required.
A 4kByte Flash/EE Data Memory space is also provided on-chip.
T his may be used as a general-purpose nonvolatile scratchpad
area. User access to this area is via a group of six SFRs. T his space
can be programmed at a byte level, although it must first be
erased in 4-byte pages.
ADuC834 Flash/E E Memory Reliability
T he Flash/EE Program and Data Memory arrays on the
ADuC834 are fully qualified for two key Flash/EE memory
characteristics, namely
F lash/E E Memory C ycling
E ndurance
and
F lash/E E Memory Data Retention.
E ndurance
quantifies the ability of the Flash/EE memory to
be cycled through many Program, Read, and Erase cycles. In
real terms, a single endurance cycle is composed of four inde-
pendent, sequential events. T hese events are defined as:
a. initial page erase sequence
b. read/verify sequence
c. byte program sequence
d. second read/verify sequence
In reliability qualification, every byte in both the program
and data Flash/EE memory is cycled from 00 hex to FFhex
until a first fail is recorded signifying the endurance limit of the
on-chip Flash/EE memory.
As indicated in the specification pages of this data sheet,
the ADuC834 Flash/EE Memory Endurance qualification has
been carried out in accordance with JEDEC Specification
A117 over the industrial temperature range of
–
40
°
C, +25
°
C,
and +85
°
C. T he results allow the specification of a minimum
endurance figure over supply and temperature of 100,000 cycles,
with an endurance figure of 700,000 cycles being typical of
operation at 25
°
C.
Retention
quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the ADuC834
has been qualified in accordance with the formal JEDEC Re-
tention Lifetime Specification (A117) at a specific junction
temperature (T
J
= 55
°
C). As part of this qualification proce-
dure, the Flash/EE memory is cycled to its specified endurance
limit described above, before data retention is characterized.
T his means that the Flash/EE memory is guaranteed to retain
its data for its full specified retention lifetime every time the
Flash/EE memory is reprogrammed. It should also be noted
that retention lifetime, based on an activation energy of
0.6 eV, will derate with T
J
as shown in Figure 26.
A single Flash/EE
Memory
Endurance Cycle
40
60
70
90
T
J
JUNCTION TEMPERATURE
C
R
250
200
150
100
50
0
50
80
110
300
100
ADI SPECIFICATION
100 YEARS MIN.
AT T
J
= 55 C
Figure 26. Flash/EE Memory Data Retention