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參數(shù)資料
| 型號： | ADUC834BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU |
| 中文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 14 X 14 MM, MO-022-AC-1, MQFP-52 |
| 文件頁數(shù)： | 49/72頁 |
| 文件大小： | 1451K |
| 代理商： | ADUC834BS |
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REV.
P
rC (12 March 2002)
ADuC834
–
49
–
PRELIMINARY TECHNICAL DATA
WDC ON
SFR Address
Power-On Default Value
Bit Addressable
Watchdog T imer C ontrol Register
C0H
10H
Yes
T able X IX . WDCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
PRE3
PRE2
PRE1
PRE0
Watchdog T imer Prescale Bits.
T he Watchdog timeout period is given by the equation: t
WD
= (2
PRE
×
(2
9
/f
PLL
))
(0
≤
PRE
≤
7; f
PLL
= 32.768 kHz)
PRE3
PRE2
PRE1
PRE0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
PRE3
–
0 > 1001
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog will generate an interrupt response instead of a
system reset when the watchdog timeout period has expired. T his interrupt is not disabled by
the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not
being used to monitor the system, it can alternatively be used as a timer. T he prescaler is used to
set the timeout period in which an interrupt will be generated. (See also Note 1, T able X X X IX
in the Interrupt System section.)
Watchdog Status Bit.
Set
by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared
by writing a
‘
0
’
or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set
by user to enable the watchdog and clear its counters. If a
‘
1
’
is not written to this bit
within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on
WDIR.
Cleared
under the following conditions, User writes
‘
0,
’
Watchdog Reset (WDIR =
‘
0
’
);
Hardware Reset; PSM Interrupt.
Watchdog Write Enable Bit.
T o write data into the WDCON SFR involves a double instruction sequence. T he WDWR bit
must be set and the very next instruction must be a write instruction to the WDCON SFR.
e.g.,
CLR
EA
; disable interrupts while writing
; to WDT
SETB
WDWR
; allow write to WDCON
MOV
WDCON, #72h
; enable WDT for 2.0s timeout
SETB
EA
; enable interrupts again (if rqd)
T imout Period (ms)
15.6
31.2
62.5
125
250
500
1000
2000
0.0
Action
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
3
WDIR
2
WDS
1
WDE
0
WDWR
WAT CHDOG T IME R
T he purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC834
enters an erroneous state, possibly due to a programming
error, electrical noise, or RFI. T he Watchdog function can be
disabled by clearing the WDE (Watchdog Enable) bit in the
Watchdog Control (WDCON) SFR. When enabled; the watchdog
circuit will generate a system reset or interrupt (WDS) if the user
program fails to set the watchdog (WDE) bit within a predeter-
mined amount of time (see PRE3
–
0 bits in WDCON). T he
watchdog timer itself is a 16-bit counter that is clocked at
32.768 kHz. T he watchdog time-out interval can be adjusted
via the PRE3
–
0 bits in WDC ON. Full Control and Status of
the watchdog timer function can be controlled via the watch-
dog timer control SFR (WDCON). T he WDCON SFR can
only be written by user software if the double write sequence
described in WDWR below is initiated on every write access to
the WDCON SFR.
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| ADUC834BSZ | 功能描述:IC ADC DUAL16/24BIT W/MCU 52MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
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