
(12 March 2002) REV.
P
rC
ADuC834
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36
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PRELIMINARY TECHNICAL DATA
AD C C hopping
Both ADC s on the ADuC 834 implement a chopping scheme
whereby the ADC repeatability reverses its inputs. T he deci-
mated digital output words from the Sinc
3
filters therefore have a
positive offset and negative offset term included.
As a result, a final summing stage is included in each ADC so that
each output word from the filter is summed and averaged with the
previous filter output to produce a new valid output result to
be written to the ADC data SFRs. In this way, while the
ADC throughput or update rate is as discussed earlier and
illustrated in T able VIII, the full settling time through the ADC
(or the time to a first conversion result), will actually be given
by 2
×
t
ADC
.
T he chopping scheme incorporated in the ADuC834 ADC re-
sults in excellent dc offset and offset drift specifications and
is extremely beneficial in applications where drift, noise rejec-
tion, and optimum EMI rejection are important factors.
C alibration
T he ADuC834 provides four calibration modes that can be
programmed via the mode bits in the ADCMODE SFR de-
tailed in T able V. In fact, every ADuC 834 has already been
factory calibrated. T he resultant Offset and Gain calibration
coefficients for both the primary and auxiliary ADC s are
stored on-chip in manufacturing-specific Flash/EE memory
locations. At power-on, these factory calibration coefficients
are automatically downloaded to the calibration registers in
the ADuC834 SFR space. Each ADC (primary and auxiliary)
has dedicated calibration SFRs, these have been described earlier
as part of the general ADC SFR description. However, the
factory calibration values in the ADC calibration SFRs will be
overwritten if any one of the four calibration options are initiated
and that ADC is enabled via the ADC enable bits in
ADCMODE.
Even though an internal offset calibration mode is described
below, it should be recognized that both ADCs are chopped. T his
chopping scheme inherently minimizes offset and means that
an internal offset calibration should never be required. Also, be-
cause factory 5 V/25°C gain calibration coefficients are
automatically present at power-on, an internal full-scale cali-
bration will only be required if the part is being operated at 3 V or
at temperatures significantly different from 25°C.
T he ADuC834 offers “internal” or “system” calibration facili-
ties. For full calibration to occur on the selected ADC, the
calibration logic must record the modulator output for two
different input conditions. T hese are “zero-scale” and “full-
scale” points. T hese points are derived by performing a
conversion on the different input voltages provided to the
input of the modulator during calibration. T he result of the
“zero-scale” calibration conversion is stored in the Offset
C alibration Registers for the appropriate ADC . T he result of
the “full-scale” calibration conversion is stored in the Gain
Calibration Registers for the appropriate ADC. With these
readings, the calibration logic can calculate the offset and the
gain slope for the input-to-output transfer function of the
converter.
During an “internal” zero-scale or full-scale calibration, the re-
spective “zero” input and “full-scale” input are automatically
connected to the ADC input pins internally to the device. A
“system” calibration, however, expects the system zero-scale and
system full-scale voltages to be applied to the external ADC
pins before the calibration mode is initiated. In this way external
ADC errors are taken into account and minimized as a result of
system calibration. It should also be noted that to optimize
calibration accuracy, all ADuC834 ADC calibrations are car-
ried out automatically at the slowest update rate.
Internally in the ADuC834, the coefficients are normalized before
being used to scale the words coming out of the digital filter. T he
offset calibration coefficient is subtracted from the result prior to
the multiplication by the gain coefficient. All ADuC834 ADC
specifications will only apply after a zero-scale and full-scale
calibration at the operating point (supply voltage/temperature)
of interest.
From an operational point of view, a calibration should be treated
like another ADC conversion. A zero-scale calibration (if re-
quired) should always be carried out before a full-scale calibration.
System software should monitor the relevant ADC RDY 0/1
bit in the ADC ST AT SFR to determine end of calibration
via a polling sequence or interrupt driven routine.